Automated book layout in static CMOS

Details Automated book layout in static CMOS Automated book layout in static CMOS

1985-03-01

1987-10-13

Harkcom, Gary V.

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364491, H03K 1909

Patent

active

047003162

ABSTRACT:
A method of generating the layout of CMOS cells from a high-level functional description of the cells, as well as generating the particular details of the CMOS device. In particular, the image of the chip is formed having the polysilicon gates of the transistors on the n-side vertically aligned with those of the p-side vertically aligned with those of the p-side to minimize the wiring effort. The interconnections between the source and drains are orthogonal to the gates, and run along one layer of metal.

REFERENCES:
patent: 4584653 (1986-04-01), Chih et al.
patent: 4591993 (1986-05-01), Griffin et al.

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