Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-09-28
2001-05-29
Powell, William (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C216S038000, C438S719000, C438S721000, C438S745000
Reexamination Certificate
active
06239037
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a self-aligned etching process for providing word lines and improving the reliability of electronic memory devices integrated on semiconductor substrates displaying a matrix type topography comprising word lines and bit lines.
Specifically the present invention relates to a self-aligned etching process for providing a plurality of parallel word lines in a first conducting layer deposited over a planarized architecture obtained starting from a semiconductor substrate on which is provided a plurality of active elements extending along separate parallel lines, e.g. bit lines, for memory cell comprising gate regions formed by a first conducting layer, an interpoly dielectric layer and a second conducting layer, said gate regions being insulated from each other by at least one insulation region to form this architecture with said word lines being defined photolithographically by protective strips.
The present invention also relates to a memory device with matrix configuration of the cross-point type and comprising bit lines and word lines.
The present invention concerns specifically but not exclusively a self-aligned etching process for providing word lines in electronic memories integrated on contactless semiconductor and with a virtual ground circuitry. The following description is given with reference to this specific field of application with the only purpose of simplifying its explanation.
BACKGROUND OF THE INVENTION
As is well known, EPROM or FLASH-EPROM electronic memory devices require the provision on a semiconductor substrate of a matrix-type topography in which a plurality of bit lines having a floating gate region is intersected above by a plurality of conducting strips properly called word lines
A topography of this type is shown in the photograph of
FIG. 1
obtained by electronic microscopy techniques.
The conventional provision of this matrix-type topography is not entirely without problems and shortcomings because it was verified experimentally that it is possible that the floating gate regions may find themselves contacted by spurious residues of conducting materials not entirely removed during manufacturing.
In the following description given by way of examples there are again proposed the process steps necessary for defining on a semiconductor substrate a matrix-type topography of an EPROM memory device comprising word lines, bit lines and floating gate regions to better carify those aspects necessary for explaining the technical problems.
Starting from a semiconductor substrate
1
, e.g., like that shown in
FIG. 2
, in which there is already a division into active areas with the possible presence of a field oxide dividing layer
2
, and multiple depositions are made over the entire surface of the substrate.
First a thin gate oxide layer
3
is deposited. Then a deposition of a first polysilicon layer
4
, identified by the name POLY1, is provided followed by a deposition of a second dielectric interpoly layer
5
, e.g., oxide-nitride-oxide or ONO, which is encapsulated above by another deposition of a third polysilicon layer
6
which is identified by the name POLY CAP.
At this point a masked photolithography step which for convenience is identified by the name ‘POLY1 mask’ defines a topography of protected areas forming the gate regions and related bit lines.
A cascade self-aligned etching allows removal of parallel strips of multiple layers until reaching the active areas of the substrate
1
.
This cascade etching removes from the unprotected areas of the photolithography the POLY CAP layer
6
, the ONO layer
5
, the POLY1 layer
4
, the gate oxide layer
3
and the field oxide
2
if necessary where present.
This defines a spatial geometry on the semiconductor substrate
1
in which it is possible to recognize a plurality of active elements extending along separate parallel lines, e.g., memory cell bit lines
13
, and corresponding gate regions.
The gate regions
13
are formed as shown in
FIG. 2
by a stratified structure of POLY CAP-ONO-POLY1-gate oxide and possibly field oxide, as shown in FIG.
2
.
During this self-aligned etching, removal of the POLY CAP layer
6
causes deposition of polymers which create a pair of steps or ribs
10
on the underlying POLY1 layer
4
which thus projects laterally with respect to the layers deposited above as shown in
FIGS. 2 and 4
.
Another cause which could be at the origin of the formation of this pair of steps
10
is generally an additional oxidation step usually used for sealing the bit lines
13
. During this oxidation step the POLY CAP layer
6
can reoxidize more than the POLY1 layer
4
(depending on the type of doping of the POLY1) as shown in FIG.
2
.
The above-mentioned steps
10
made up of the POLY1 layer
4
projecting laterally can originate a short circuit between adjacent floating gate regions once a self-aligned etching has been completed to define word lines and hence individual memory cells.
FIG. 3
shows an electronic microscope photograph of a semiconductor substrate having a matrix-type topography after performance of a self-aligned etching to define the word lines, which can be identified in the high-luminosity areas which are united by thin white strips revealing the presence of the steps
10
.
The successive process steps for the provision of an EPROM memory device call for the use of a planarization method in which a first insulating dielectric film
8
and a second planarizing dielectric film
7
deposited in the interstitial regions included between the gate regions
13
allow obtaining a planarized architecture
9
as shown in FIG.
2
.
It is important to note that the above described process causes the first insulating dielectric film
8
to act as a protective micromask for the step
10
created previously.
Provision of the plurality of word lines intersecting the gate regions
13
calls for deposition of a conducting layer entirely covering the planarized architecture
9
as shown in FIG.
4
.
This conducting layer can be obtained by means of successive deposition of a protective layer
12
, e.g., of polysilicon and indicated for convenience by the name POLY2, and a final layer
11
of silicide, e.g., tungsten silicide.
To define the spatial geometry of the word lines there is again made use of a conventional photolithography step with an appropriate mask usually indicated as a POLY2 mask designating unprotected areas in which a self-aligned etching can be performed even for the word lines.
Another objective of this etching is to mutually insulate the individual memory cells by removing material from the floating gate regions not protected by the photolithography step.
Those skilled in the art usually perform this self-aligned etching in two successive steps and with a vertical profile.
The first step calls for removal of the conducting layer
11
,
12
and the underlying POLYCAP layer
6
while the second step calls for removal of the ONO layer
5
and POLY1 layer
4
.
FIG. 5
shows a vertical cross section of an electronic memory devices comprising gate regions
13
planarized by means of insulation regions
7
and
8
after performance of the first self-aligned etching step for a definition of the word lines and memory cells.
This cross section was taken in a region included between two consecutive word lines in which erosion takes place due to the first self-aligned etching step.
In this Figure it can readily be seen that the insulation regions
7
and
8
are only partially etched because the dielectric layer
5
at the end of this etching is still protected by the insulating dielectric film
8
.
It is accordingly clear that the step zone
10
is still presented.
The second self-aligned etching step, which is diagrammed in the cross section of
FIG. 6A
only for the removal of the dielectric layer
5
, is insufficient to eliminate the steps
10
if done with a vertical profile.
The final removal of the POLY1 layer
4
with a vertical profile etching is insufficient to remove the step zone
10
because of the persistence of the
Colabella Elio
Pividori Luca
Rebora Adriana
Galanthay Theodore E.
Iannucci Robert
Powell William
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
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