Amplifiers – With periodic switching input-output
Reexamination Certificate
2001-09-04
2002-12-24
Pascal, Robert (Department: 2817)
Amplifiers
With periodic switching input-output
C330S051000, C327S124000
Reexamination Certificate
active
06498530
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of ping-pong amplifiers, and particularly to techniques for reducing transient switching errors for such amplifiers.
2. Description of the Related Art
Auto-zeroed ping-pong amplifiers are known to provide low input offset voltages. A schematic diagram of a basic ping-pong amplifier
10
is shown in
FIG. 1
a
. Two amplifiers A
1
and A
2
, each of which has differential inputs and outputs, receive a differential input signal made up of signals INP and INM. Each amplifier also includes a common-mode reference voltage input CMR connected to receive a common-mode reference voltage VCMR, and a common-mode feedback circuit. The common-mode feedback circuit sets the amplifier's common-mode output voltage—given by the sum of its differential outputs divided by 2—so that each of its outputs is nominally set to VCMR when the differential output voltage is zero. VCMR is typically set to a value between the amplifier's power rails so that the amplifier may have a high gain.
The ping-pong amplifier also includes an output amplifier A
0
, which is connectable to the outputs of A
1
via a pair of switches S
1
and S
2
, or to the outputs of A
2
via a pair of switches S
3
and S
4
. A
0
has a compensation capacitor CC connected from its output to its inverting input, and provides the ping-pong amplifier's single-ended output OUT. A pair of fully differential nulling amplifier's A
3
and A
4
are used to auto-zero A
1
and A
2
, respectively; the inputs of A
3
and A
4
are connected to the outputs of A
1
and A
2
via pairs of switches S
5
/S
6
and S
7
/S
8
, respectively. A pair of memory capacitors C
1
and C
2
are connected to the inputs of A
3
, and memory capacitors C
3
and C
4
are connected to A
4
's inputs. A switch S
9
is connected between the inputs of A
1
, and a switch S
10
is connected between the inputs of A
2
. A switch S
11
is connected between INM and A
1
, and a switch S
12
is connected between INM and A
2
.
The switches are controlled with a control circuit (not shown), which operates them in accordance with the timing diagram shown in
FIG. 1
a
. The ping-pong amplifier has a two-phase timing cycle. During the first phase (&phgr;1), switches S
5
, S
6
and S
9
are closed, such that amplifier A
1
is auto-zeroed by the output currents of nulling amplifier A
3
, with the error signals stored on memory capacitors C
1
and C
2
. Switches S
3
, S
4
and S
12
are also closed during &phgr;1, allowing the differential input signal to be amplified by A
2
followed by A
0
. The roles are reversed during the second phase (&phgr;2): switches S
7
, S
8
and S
10
are closed such that A
2
is auto-zeroed by A
4
(with the error signals stored on memory capacitors C
3
and C
4
), and switches S
1
, S
2
and S
11
are closed such that the input signal is amplified by A
1
followed by A
0
.
As noted above, amplifiers A
1
and A
2
each include common-mode feedback circuits which nominally set their common-mode output voltages to VCMR when their differential output voltages are zero. One weakness in this arrangement is that mismatch in the common-mode feedback circuit can result in common-mode output voltages which differ from VCMR. For example, A
1
and A
2
may produce common-mode output voltages VCMR
1
and VCMR
2
, respectively, and due to mismatch, VCMR≠VCMR
2
.
A possible cause for this type of mismatch is illustrated in
FIG. 1
b
, which shows one possible implementation of a fully differential amplifier such as A
1
or A
2
: transistors M
1
-M
4
and current sources I
0
-I
2
form an operational amplifier, and transistors M
5
-M
11
and current source I
3
form a common-mode feedback circuit. If the average op amp output is higher than VCMR, more current flows through M
10
and M
11
into M
7
, which causes M
5
and M
6
to pull the output voltages back down. However, any mismatch between transistors M
8
-M
11
can result in the common-mode output voltage differing from VCMR, and hence VCMR
1
and VCMR
2
voltages which are not equal.
Referring back to
FIG. 1
a
, when VCMR
1
≠VCMR
2
, and the timing cycle transitions from &phgr;1 to &phgr;2, the voltage at the inverting input of A
0
changes from approximately VCMR
1
to VCMR
2
, which injects a transient with an amplitude about equal to VCMR
1
-VCMR
2
into compensation capacitor CC. Similarly, a transient with an amplitude about equal to VCMR
2
-VCMR
1
is injected into CC when the timing cycle transitions from &phgr;2to &phgr;1. As shown in
FIG. 1
a
's timing diagram, these transients appear in the ping-pong amplifier's output, which reduces the fidelity of the output signal.
SUMMARY OF THE INVENTION
A ping-pong amplifier and method are presented which overcome the problems noted above. Differences between VCMR
1
and VCMR
2
are reduced, which reduces switching transients that might otherwise appear in the amplifier's output.
The novel ping-pong amplifier includes an error amplifier, which has one input connected to common-mode reference voltage VCMR, its other input switchably connected to the common-mode output of one of the two differential amplifiers A
1
and A
2
, and an output which is switchably connected to the common-mode reference voltage inputs of A
1
and A
2
. Respective storage devices, preferably memory capacitors, are also connected to the two common-mode reference voltage inputs.
In operation, the error amplifier's input is periodically connected to the common-mode output of A
1
, and its output is connected to A
1
's common-mode reference (CMR) voltage input. This arrangement forms a closed-loop which forces A
1
's common-mode output voltage to be equal to VCMR; the error amplifier's output voltage is stored on the memory capacitor connected to the A
1
's CMR input. Similarly, the error amplifier's input and output are periodically connected to the A
2
's common-mode output and common-mode reference input, respectively, to force A
2
's common-mode output voltage to be equal to VCMR, with the error amplifier's output voltage stored on the memory capacitor connected to the A
2
's common-mode reference voltage input.
The voltages stored on the memory capacitors connected to the CMR inputs continuously adjust the common-mode output voltages of A
1
and A
2
so that VCMR
1
and VCMR
2
are held equal to VCMR. Keeping VCMR
1
=VCMR
2
=VCMR ensures that transients due to mismatch in the common-mode feedback circuits are largely reduced.
The invention is preferably used in an auto-zeroing configuration, which further improves the amplifier's performance.
Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings.
REFERENCES:
patent: 4931745 (1990-06-01), Goff et al.
patent: 5115202 (1992-05-01), Brown
patent: 5847600 (1998-12-01), Brooks et al.
patent: 6121831 (2000-09-01), Mack
patent: 6140872 (2000-10-01), McEldowney
patent: 6407630 (2002-06-01), Yao et al.
IEEE Journal of Solid-State Circuits,A Rail-to-Rail Ping-Pong OP-AMP,Ion E. Opris and Gregory T.A. Kovacs, vol. 31, No. 9, Sep. 1996, pp. 1320-1324.
Analog Devices Inc.
Koppel, Jacobs Patrick & Heybl
Nguyen Khanh Van
Pascal Robert
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