Auto-zero sample and hold circuit

Details Auto-zero sample and hold circuit Auto-zero sample and hold circuit

1984-08-27

1986-05-06

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307491, 307494, G11C 2702

Patent

active

045874433

ABSTRACT:
A sample and hold circuit contains a pair of differential amplifiers (A1 and A2) switchably arranged in series. The circiut input signal (V.sub.IN) during sample is provided to the first amplifier (A1) which is coupled to a storage capacitor (C). The second amplifier (A2) provides the circuit output signal (V.sub.OUT) during hold. Switching circuitry (S1, S2, and S3) enables the input and output signals to undergo the same transfer function in the first amplifier. The voltage offset of the first amplifier is thereby cancelled out of the output signal, while the effect of the voltage offset of the second amplifier is reduced drastically so as to provide excellent auto-zeroing.

REFERENCES:
patent: 3696305 (1972-10-01), Mitchell et al.
patent: 4119960 (1978-10-01), Hill
patent: 4302689 (1981-11-01), Brodie
patent: 4404479 (1983-09-01), Toyomaki
patent: 4439693 (1984-03-01), Lucas et al.
F. Gasparik, "An Autozeroing Sample and Hold IC," 1980 IEEE Int'l Solid-State Circs. Conf., Dig. Tech. Paps., Feb. 1980, pp. 132-133.

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