Active solid-state devices (e.g. – transistors – solid-state diode – Responsive to non-electrical signal
Reexamination Certificate
2001-11-02
2004-05-11
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Responsive to non-electrical signal
C257S421000, C438S048000, C438S049000
Reexamination Certificate
active
06734511
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor devices and manufacturing methods and systems thereof. More specifically, the present invention relates to semiconductor chips, which are based on via/contact configurations. The present invention also relates to semiconductor chips having variable functions.
BACKGROUND OF THE INVENTION
Modern electronic devices utilize semiconductor chips, commonly referred to as “integrated circuits” which incorporate numerous electronic elements. These chips can be mounted on substrates, which physically support the chips and electrically interconnect each chip with other elements of the circuit. The substrate may be a part of a discrete chip package used to hold a single chip and equipped with terminals for interconnection to external circuit elements. Such substrates may be secured to an external circuit board or chassis.
Alternatively, in a so-called “hybrid circuit” one or more chips can be mounted directly to a substrate forming a circuit panel arranged to interconnect the chips and the other circuit elements mounted to the substrate. In either case, the chip must be securely held on the substrate and must be provided with reliable electrical interconnection to the substrate. The interconnection between the chip itself and its supporting substrate is commonly referred to as “first level” assembly or chip interconnection, as distinguished from the interconnection between the substrate and the larger elements of the circuit, commonly referred to as a “second level” interconnection.
The structures utilized to provide the first level connection between the chip and the substrate must accommodate all of the required electrical interconnections to the chip. The number of connections to external circuit elements, commonly referred to as “input-output” or “I/O” connections, is determined by the structure and function of the chip. Advanced chips capable of performing numerous functions may require substantial numbers of I/O connections.
The size of the chip and substrate assembly is a major concern. The size of each such assembly influences the size of the overall electronic device. More compact assemblies, with smaller distances between chips provide smaller signal transmission delays and hence permit faster operation of the devise.
First level interconnection structures connecting a chip to a substrate ordinarily can be subject to substantial strain caused by thermal cycling as temperatures within the device change during operation. The electrical power dissipated within the chip tends to heat the chip and substrate, so that the temperatures of the chip and substrate rise each time the device is turned on and fall each time the device is turned off.
As the chip and the substrate ordinarily can be formed from different materials having different coefficients of thermal expansion, the chip and substrate ordinarily expand and contract by different amounts. This causes the electrical contacts on the chip to move relative to the electrical contact pads on the substrate as the temperature of the chip and substrate changes. This relative movement deforms the electrical interconnections between the chip and substrate and places them under mechanical stress. These stresses can be applied repeatedly with repeated operation of the device, and can cause breakage of the electrical interconnections. Thermal cycling stresses may occur even where the chip and substrate can be formed from like materials having similar coefficients of thermal expansion, because the temperature of the chip may increase more rapidly than the temperature of the substrate when power is first applied to the chip.
During the process of semiconductor fabrication, alternating layers of a nonconducting material (dielectric), such as silicon dioxide, and of a conductor, such as aluminum tungsten, can be formed over the semiconductor substrate. Devices, such as transistors or diodes, among others, can be formed at and within the semiconductor substrate. Contact between the lowest layer of conductive material and a region of a device, at and within the semiconductor device (e.g., a source or drain) is generally made through an opening in a first dielectric layer. The opening can then be filled with a conductive material to form a contact that couples the region of the device to the lowest conductive layer. In addition, a vertical opening, known as a via, is filled with conductive material to connect circuits on various layers of a device to one another and to the semiconductor substrate. This conductive material is known as an interconnect.
Openings (i.e., vias and contacts) are often formed using a mask and photolithography. For example, a photosensitive film, such as photoresist, is applied to a surface of the semiconductor substrate. A mask with a desired pattern is used during photolithography to help transfer the desired pattern onto the substrate or a surface on the substrate. The photoresist is then exposed to light through the mask and then developed. The exposed surface of the substrate and photoresist can be removed so that the desired pattern is now on the substrate's surface.
In the manufacture of semiconductor devices, metal vias and contacts thus can be deposited into via openings and contact holes on semi-conducting wafers that have been preprocessed. Semiconductor devices are thus formed connected to each other by the metal vias and contacts to form an integrated circuit. In particular, aluminum, aluminum alloys, tungsten and tungsten alloys are frequently used for deposition into the via openings and contact holes on the semi-conducting substrate. These deposition processes can be carried out by a physical vapor deposition (or sputtering) or a chemical vapor deposition technique.
The cost of the chip and substrate assembly is also a major concern. All these concerns, taken together, present a formidable engineering challenge. Various attempts have been made heretofore to provide primary interconnection structures and methods to meet these concerns, but none of these is truly satisfactory in every respect.
Vias and contacts currently are utilized as a link between multi-layer conductors and devices thereof, regardless of preparation by wet or dry etching, dual damascene, or filling by tungsten, aluminum or copper, and so forth. Physically, vias and contacts have a common characteristic of immovability at fixed positions, but do not generally provide any functions other than that of linking. Consequently, if a semiconductor chip is required to provide various functions by extrinsic environmental conditions, it may be necessary to attach one or sensors to the semiconductor chip, which in turn increases associated costs, volume and additionally, the complexity of design.
Based on the foregoing, the present inventors have discovered that a need exists for a method and system which would result in a shrinkage in total dimension, a cost reduction, and a decreased complexity of circuit design, while providing a unique variable function feature for a single semiconductor chip and associated circuit thereof. The present invention thus meets this need through the implementation of a function switch, along with associated methods and systems thereof.
BRIEF SUMMARY OF THE INVENTION
The following summary of the invention is provided to facilitate an understanding of some of the innovative features unique to the present invention, and is not intended to be a full description. A full appreciation of the various aspects of the invention can be gained by taking the entire specification, claims, drawings, and abstract as a whole.
It is therefore one aspect of the present invention to provide an improved semiconductor chip and associated circuitry thereof.
It is another aspect of the present invention to provide a semiconductor chip based on a via/contact configuration.
It is yet another aspect of the present invention to provide a method and system for implementing a variable function circuit within a single semiconductor chip.
It is yet another aspect of the pre
Kuo Chiu-Bian
Liu Jun-Xiu
Peng Chun-Hsiung
Yen Ming-Shuo
Flynn Nathan J.
Mondt Johannes P
Taiwan Semiconductor Manufacturing Co. Ltd.
Tung & Associates
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