Auto-ranging phase-locked loop

Details Auto-ranging phase-locked loop Auto-ranging phase-locked loop

2006-09-28

2008-10-21

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

C331S011000, C331S016000, C331S017000, C331S025000, C331SDIG002, C327S159000

Reexamination Certificate

active

07439812

ABSTRACT:
A phase locked loop circuit includes an oscillator, a dividing circuit coupled to the oscillator having a controllable dividing factor, and a rangefinder circuit coupled to the dividing circuit. The rangefinder circuit is configured to control the dividing factor in response to an operating characteristic of the phase-locked loop circuit.

REFERENCES:
patent: 6486857 (2002-11-01), Esaki et al.
patent: 6686804 (2004-02-01), Adams et al.
patent: 7245191 (2007-07-01), Sanders
patent: 2001/0015677 (2001-08-01), Choi
Y. Fouzar, et al., “Very short locking time PLL based on controlled gain technique”, ICECS 2000—IEEE International Conference on Electronics, Circuits and Systems, Dec. 17-20, 2000, vol. 1, pp. 252-255.
Y. Fouzar, et al., “A New Fully Integrated CMOS Phase-Locked Loop with Low Jitter and Fast Lock Time”, ISCAS 2000—IEEE International Symposium on Circuits and Systems, May 28-31, 2000, vol. 2, pp. 253-256.
“Phase-locked loop”, http://en.wikipedia org/wiki/Phase-locked loop, May 29, 2006, 10 pages.
1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer, Cypress Advance Information, Feb. 12, 2004, 9 pages.

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