Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular power supply distribution means
Reexamination Certificate
1998-11-23
2002-05-14
Fahmy, Wael (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular power supply distribution means
C438S129000, C345S098000, C345S100000
Reexamination Certificate
active
06388277
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an auto placement and routing device for laying out wiring in a semiconductor integrated circuit, and the semiconductor integrated circuit including the wiring laid out by the auto placement and routing device.
2. Background of the Invention
On the substrate of the semiconductor integrated circuit, a plurality of wires such as a signal line, a source wire and a ground wire are formed. The layout of wiring is determined by the auto placement and routing device. Each wire forms a capacitance between the substrate or the other wire and itself, called a wiring capacitance, as well as having an electrical resistance called a wiring resistance. When a signal is propagated through a signal line, a delay is caused according to a value determined by the product of the wiring resistance and the wiring capacitance of that signal line. If the wiring resistance is disregarded, the delay of the signal is determined by the wiring capacitance.
More specifically, the wiring capacitance equals to a total of a capacitance between the upper or bottom surface of the wire and the substrate (capacitance due to a plane component), a capacitance between the side surface of the wire and the substrate (fringe capacitance), and a capacitance between the adjacent wires (coupling capacitance).
In a semiconductor integrated circuit which was made before the design rule reached a submicron level, the capacitance between the wire and the substrate, especially, the capacitance due to a plane component, formed a large proportion of the wiring capacitance, while the coupling capacitance formed a small proportion thereof. In addition, since the potential of the substrate was unchanged, there was no necessity of considering that the amount of signal delay due to the wiring capacitance may fluctuate with a change in the potential of the substrate.
However, with recent downsizing of the semiconductor integrated circuit, the upper or bottom surface area of the wire becomes small and an interval between the adjacent wires is reduced. This reduces the proportion of the capacitance due to a plane component in the wiring capacitance, while increasing the proportion of the coupling capacitance. To be more specific, the proportion of the coupling capacitance in the whole wiring capacitance has increased to 50% or more. Further, while the potential of the substrate is unchanged, the potential of the wire, especially of the signal line, makes a transition according to the state of a propagated signal. Thus, with the potential transition of the signal line, there occur fluctuations in the amount of signal delay due to the coupling capacitance between that signal line and the adjacent signal line. When the potential transitions of the adjacent two signal lines take place at the same time but in different ways (for example, when the potential of one signal line makes a high to low transition while the potential of the other signal line makes a low to high transition), there arises a problem that the amount of signal delay due to the coupling capacitance between those signal lines is effectively increased.
The fluctuations in the amount of delay in the signal propagation through a signal line is, as previously described, caused by fluctuations in a potential difference between that signal line and the adjacent signal line. However, it can be also considered that the cause is an increase in the coupling capacitance between those signal lines due to the potential transition of the adjacent signal line. In the specification, the coupling capacitance considered with such an increase is referred to as an “effective coupling capacitance.”
Next, timing of a signal transition will be described. In the present semiconductor integrated circuit, a signal propagated through each signal line, in most cases, makes a transition at a time when a reference signal (in general, a clock) makes a transition. The timing of each signal transition in relation to the timing of the clock transition can be considered as a matter of an attribute (signal attribute) of the signal line. For example, a signal line for propagating a signal that makes a transition at the same time that the clock makes a transition, is referred to as a “signal line having a signal attribute U,” while a signal line for propagating a signal that makes a transition with a phase difference of a half cycle of the clock as compared with the timing of the clock transition, is referred to as a “signal line having a signal attribute V.” In this way of thinking, the potential transitions of the signal lines each having a different signal attribute do not take place at the same time, while the potential transitions of the signal lines having the same signal attribute take place at the same time.
FIG. 17
schematically shows an example of a wiring layout by a conventional auto placement and routing device. For the simplicity of the description, only seven signal lines
102
1
to
102
7
are shown. Grids
101
1
to
101
13
are virtual wiring areas placed side by side on the substrate of the semiconductor integrated circuit. The auto placement and routing device allots the signal lines
102
1
to
102
7
to the grids
101
1
,
101
3
,
101
5
,
101
7
,
101
9
,
101
11
, and
101
13
, respectively. All the signal lines
102
1
to
102
7
have the same signal attribute A. Thus, on the substrate of the semiconductor integrated circuit, a plurality of signal lines
102
1
to
102
7
having the same signal attribute A are placed side by side.
FIG. 18
is a timing chart illustrating a state of each transition of signals propagated through the signal lines
102
1
to
102
7
, respectively. Since the signal lines
102
1
to
102
7
have the same signal attribute A, all the signals propagated through those signal lines
102
1
to
102
7
make transitions at an observed time T
100
. In this case, the signals propagated through the signal lines
102
1
to
102
3
and
102
5
to
102
7
make transitions from their low level (e.g., 0V) to their high level (e.g., 2.5 V), while the signal propagated through the signal line
102
4
makes a high to low transition. With the signal transitions, the potentials of the signal lines
102
1
to
102
7
also make transitions.
Noting the signal lines
102
3
and
102
4
, we will now describe fluctuations in the effective coupling capacitance accompanied by the potential transitions of the signal lines. As shown in
FIG. 18
, before the observed time T
100
, the potential of the signal line
102
3
was 0V and the potential of the signal line
102
4
was 2.5 V. That is, a potential difference between those signal lines was 2.5 V. However, the potential transitions of the signal lines
102
3
and
102
4
from 0 to 2.5 V and from 2.5 to 0 V, respectively, at the observed time T
100
causes an apparent potential difference of 5 V therebetween. That is, at the moment of the potential transitions, the potential difference is increased to twice the value before the transitions. This doubles the effective coupling capacitance between the signal lines
102
3
and
102
4
as compared with the value before the potential transitions. Since the signal lines
102
3
and
102
4
are allotted at two grid intervals as shown in
FIG. 17
, an increase in the effective coupling capacitance accompanied by the potential transitions of those signal lines is expressed by C/2 where C is a coefficient of the coupling capacitance.
Since the signal lines
102
1
to
102
7
have the same signal attribute A as previously described, the signals propagated through the signal lines
102
1
to
102
7
, respectively, make transitions at the same observed time T
100
. Thus, the increase in the effective coupling capacitance accompanied by the potential transitions of the signal lines takes place not only between the signal lines
102
4
and
102
3
but also between the signal line
102
4
and each of the other signal lines
102
1
,
102
2
,
102
5
,
102
6
,
102
7
.
FIG. 19
shows such an increase in the effective
Kobayashi Hiroyuki
Shimazu Yukihiko
Fahmy Wael
Lee Hsing-Ming
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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