Computer graphics processing and selective visual display system – Display driving control circuitry
Reexamination Certificate
1998-12-11
2001-09-11
Hjerpe, Richard (Department: 2774)
Computer graphics processing and selective visual display system
Display driving control circuitry
Reexamination Certificate
active
06288713
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to liquid crystal displays (LCDs), and more particularly to an auto mode detection circuit in LCDs which detects a vertical synchronous signal provided to a liquid crystal display module (LCM) and selects the operation mode of LCDs with the detection result.
Recently, any one of a data enable signal DE not containing synchronous signal or a data enable signal DE+SYNC containing synchronous signal is provided to a LCM according to computer manufacturers. In the prior, it has been to difficult to manually select the operation mode of a LCM using an external jumper according to the mode of the input signal which is received from a personal computer. Besides, although it manually changes the mode by using an external jumper, because there is a case that a controller of a LCM does not operate, the driving circuit of a LCM should be changed. Therefore, if it corresponds to PC manufacturers which provides the different signals to a LCM, it should supplement the function for selecting the desired mode in a controller according to the input signal.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an auto mode detection circuit in liquid crystal display devices which detects whether a vertical synchronous signal is received or not and selects any one of a DE only mode or a DE/SYNC mode according to the detection result.
According to an aspect of the present invention, there is provided to an auto mode detection circuit in liquid crystal display devices which selects one of a first mode of a DE only mode and a second mode of a DE/SYNC mode with detection of a vertical synchronous signal, comprising: clock signal generation means for receiving a main clock signal to generate a clock signal for detecting the vertical synchronous signal; vertical synchronous signal detection means for detecting the vertical synchronous signal to generate a detection signal whenever a desired number of the clock signals are provided from the clock signal generation means; selection signal generation means for receiving the detection signal from the vertical synchronous signal detection means to generate a mode selection signal; and mode selection means for receiving the mode selection signal from the selection signal generation means to select one of a signal for the first mode and a signal for the second mode.
In an embodiment of the present invention, the clock signal generation means includes a first 4-bit binary counter which is cleared by a reset signal and counts the main clock signal, thereby providing the most significant bit output of 4-bit outputs as its output signal; and a second 4-bit binary counter which is cleared by the reset signal and counts the output signal of the first counter, thereby providing the lowest significant bit output of 4-bit outputs as the clock signal to the vertical synchronous signal detection means. The vertical synchronous signal generation means includes: a first inverter for inverting the vertical synchronous signal externally received; a third 4-bit binary counter which is cleared by the reset signal, is loaded by the vertical synchronous signal inverted through the first inverter and counts the clock signal front the clock signal generation means, thereby providing a ripple carry out as its output signal whenever a selected number of the clock signals are applied to the vertical synchronous signal generation means; and a second inverter for inverting the output signal of the third counter to generate the detection signal to the mode selection signal generation portion.
In an embodiment of the present invention, the selection signal generation means includes: a D flip flop which the detection signal is applied as its clock signal, the reset signal is applied as its clear signal and a high state signal of Vcc is applied as its input signal; and a third inverter for inverting an output signal of the D flip flop to generate the mode selection signal to the mode selection means. The mode selection means includes: a first and a second multiplexers for selecting any one of the signal for the first mode and the signal for the second mode in accordance with the mode selection signal from the mode selection signal generation means.
According to another aspect of the present invention, there is provided to an auto mode detection circuit in liquid crystal display devices which selects one of a first mode of a DE only mode and a second mode of a DE/VSYNC mode with detection of a vertical synchronous signal, comprising:
clock signal generation means for receiving a main clock signal and a signal having a desired period to generate a clock signal for detecting the vertical synchronous signal; vertical synchronous signal detection means for detecting the vertical synchronous signal to generate a detection signal whenever a desired number of the clock signals are provided from the clock signal generation means; selection signal generation means for receiving the detection signal from the vertical synchronous signal detection means to generate a mode selection signal; and mode selection means for receiving the mode selection signal from the selection signal generation means to select one of a signal for the first mode and a signal for the second mode.
In another embodiment of the present invention, the clock signal generation means includes a first flip flop which a reset signal is applied as its clear signal, the main clock signal is applied as its clock signal and the signal having a desired period is provided as its input signal, thereby providing its input signal to the vertical synchronous signal detection means as the clock signal for detecting the vertical synchronous signal. The vertical synchronous signal detection means includes: a first inventer for inverting the vertical synchronous signal; and a counter which is cleared by a reset signal and is loaded by the vertical synchronous signal inverted through the first inverter to count the clock signal from the clock signal generation means and generates the detection signal indicating whether the vertical synchronous signal is received to the mode selection signal generation means, whenever a selected number of the clock signals are applied from the clock signal generation means.
In another embodiment of the present invention, the mode selection signal generation means includes: a second flip flop which a reset signal is applied as its clear signal, the main clock signal is applied as its clock signal and the detection signal of the vertical synchronous signal detection means is applied as its input signal, thereby providing the detection signal of the vertical synchronous signal detection means as its output signal at a rising edge of the main clock signal; a second inverter for inverting the output signal of the second flip flop; a third flip flop which a reset signal is applied as its clear signal, an output signal of the second inverter is applied as its clock signal and a high state signal of Vcc is applied as its input signal; a third inverter for inverting an output signal of the third flip flop to generate the mode selection signal to the mode selection means. The mode selection means includes: a first multiplexer and a second multiplexer for selecting one of the signal for the first mode and the signal for the second mode in accordance with the mode selection signal from the mode selection signal generation means.
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patent: 08248395 (1996-09-01), None
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Lee Soon Jea
Lee Yong Ho
Hjerpe Richard
Hyundai Electronics Industries Co,. Ltd.
Ladas & Parry
Laneau Ronald
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