Auto DRAM parity enable/disable mechanism

Details Auto DRAM parity enable/disable mechanism Auto DRAM parity enable/disable mechanism

1995-03-24

1997-02-25

Beausoliel, Jr., Robert W.

Excavating

371 492, G06F 1134, G06F 1110

Patent

active

056066627

ABSTRACT:
A memory control unit (MCU) detects whether each bank of a DRAM subsystem will support parity error checking, and based on this determination, selectively disables the system parity error checking for those banks which do not support parity. The MCU automatically enables the system parity error checking for any banks that do support parity error checking. The memory control unit advantageously eliminates the need for the user to know what types of DRAM are in the system or how to configure the system to operate with the current DRAM types. Furthermore, the memory control unit allows for selective generation of parity checking among DRAM banks depending upon which banks support parity. Accordingly, even if one or more DRAM banks do not support parity, the capabilities of those DRAM banks that support parity will not go unused, and the advantages attained by parity error checking will be realized for the DRAM banks that support parity.

REFERENCES:
patent: 5155735 (1992-10-01), Nash et al.
patent: 5339322 (1994-08-01), Rastegar
patent: 5355377 (1994-10-01), Venkidu et al.
patent: 5392252 (1995-02-01), Rimpo et al.

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