Auto-delay gain circuit

Details Auto-delay gain circuit Auto-delay gain circuit

1989-12-20

1990-11-27

Miller, Stanley D.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307443, 307493, 307542, 307601, H03K 513, H03K 1716

Patent

active

049738658

ABSTRACT:
A multi-stage output buffer provides for inactivation and then delayed reactivation of a second gain stage after a data transition. The delay imposed is a function of the output voltage, which is fed back through a threshold detector. A transition detector is coupled to data inputs so that it can inactivate the second gain stage upon a data transition; the transition detector is coupled to the threshold detector so that it can activate the second gain stage once the output voltage crosses a predetermined threshold voltage. This configuration imposes relatively long delays on second gain stage activation when large loads are applied to keep switching transients at tolerable levels. When lesser loads are applied, a shorter delay permits more rapid throughput.

REFERENCES:
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patent: 4529895 (1985-07-01), Garverick et al.
patent: 4570912 (1986-02-01), Yasuda et al.
patent: 4717835 (1988-01-01), Takeuchi
patent: 4760283 (1988-07-01), Weaver
patent: 4772812 (1988-09-01), Desmarais
patent: 4782252 (1988-11-01), Levy et al.
patent: 4880997 (1989-11-01), Steele

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