Coded data generation or conversion – Converter calibration or testing
Reexamination Certificate
1999-05-11
2001-03-20
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
C341S154000
Reexamination Certificate
active
06204785
ABSTRACT:
CROSS-REFERENCES TO RELATED APPLICATIONS
Not Applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
BACKGROUND OF THE INVENTION
The present embodiments relate to data converters, and are more particularly directed to converters using resistor strings.
Data converters may be used in various types of electronic circuits, or may be formed as a single integrated circuit device. Such converters typically take one of two forms, either as a digital-to-analog converter (“DAC”) or an analog-to-digital converter (“ADC”). For the DAC, its operation converts an input digital signal to an output analog signal, typically where the amplitude of the output analog signal corresponds directly to the magnitude of the input digital signal. Conversely, the ADC converts an input analog signal to an output digital signal, typically where the value of the output digital signal corresponds directly to the amplitude of the input analog signal. In many configurations, both DACs and ADCs implement a resistor string that includes a number of series-connected resistors, where each resistor provides a voltage tap at each of its ends. Typically, the overall string is biased at opposing ends by two different reference voltages, for example where one such voltage may be a positive voltage and the other is ground. Accordingly, the resistor string forms a voltage dividing network and each of the voltage taps is accessible as part of the operation for the data conversion (i.e., either from digital to analog, or analog to digital). Given this functionality, the size and speed requirements imposed on such data converters, and in an effort to maintain the linearity between the digital input and the analog output, a common concern is to endeavor to ensure that each resistor in the string has as close to the same resistance value as all other resistors in the string. The present embodiments are directed to this concern and, in providing a solution to same, improve both DAC and ADC technology.
For further background to converters and by way of example,
FIG. 1
illustrates a typical configuration of a prior art DAC
10
, and is detailed briefly below. In addition, since the primary focus of the preferred embodiments described later is directed to resistor strings as used in either a DAC or an ADC, the following discussion provides one example of such a string as used in a DAC, but is not unduly lengthened by also providing a detailed analysis of an ADC. Instead, such an understanding is left to one skilled in the art.
Turning to DAC
10
of
FIG. 1
, it includes a series-connected resistor string designated generally at
12
. By way of example and as appreciated later, DAC
10
is a 3-input 8-output DAC, while numerous other dimensions may exist for different DAC configurations. For the current example of a 3-to-8 DAC, resistor string
12
includes seven resistive elements shown as R
0
through R
6
. Resistive elements R
0
through R
6
may be formed using various techniques, where the particular technique is not critical to the present inventive teachings. A voltage source Vs is applied across resistor string
12
, and may be of any suitable biasing voltage, which for current applications is typically on the order of 1 to 5 volts. Thus, assuming the resistance of each element in the string is equal, the division of this voltage across the resistors is uniform.
Looking to the detailed connections with respect to the resistive elements in string
12
, each resistive element provides two taps from which a voltage may be measured as detailed below. For example, looking to the bottom of
FIG. 1
, resistive element R
0
provides a tap T
0
and a tap T
1
, while resistive element R
1
shares the same tap T
1
and provides another tap T
2
, and so forth. Each tap has a switching device connected between it and an output node, V
OUT
. In the current example, each of these switching devices is an n-channel field effect transistor, and is labeled for convenience by combining the abbreviation ST (i.e., switching transistor) with the same numeric identifier corresponding to the tap to which a source/drain of the transistor is connected. For example, a first source/drain of transistor ST
0
is connected to tap T
0
, a first source/drain of transistor ST
1
is connected to tap T
1
, and so forth. The second source/drain of each of the switching transistors is connected to V
OUT
. The gate of each of transistors ST
0
through ST
7
is connected to receive a control signal from a decoder
14
. Decoder
14
is connected to receive a 3-bit digital input at corresponding inputs
10
through
12
, and to enable one of eight output conductors, C
0
through C
7
, in an output bus
16
, as further detailed below.
The operation of DAC
10
is as follows. A 3-bit digital word is connected to inputs through
12
of decoder
14
, and decoder
14
includes sufficient logic circuitry or the like to respond by enabling only one of the eight output conductors, C
0
through C
7
, in output bus
16
. In a simple case, therefore, the numeric identifiers of the conductors in bus
16
may be thought of as corresponding to the value of the digital input word, that is, the corresponding numbered conductor is asserted in response to the magnitude of the 3-bit digital input word. For example, if the 3-bit digital word equals 001, then conductor C
1
of bus
16
is enabled. As another example, if the 3-bit digital word equals
101
, then conductor C
5
of bus
16
is enabled. Once a conductor in bus
16
is asserted, which in the current example occurs by asserting the conductor logically high, it enables the single switching transistor to which it is connected. By way of illustration of this operation, and continuing with the example of conductor C
1
of bus
16
being asserted, decoder
14
places a logic high signal at the gate of switching transistor ST
1
. In response, switching transistor ST
1
provides a conductive path between tap T
1
and output node V
OUT
. In addition, recall that the voltage source Vs is evenly divided across resistor string
12
; consequently, by enabling transistor ST
1
, then the divided voltage at tap T
1
is coupled to output node V
OUT
. Accordingly, the digital input of
001
has been converted to an analog voltage which equals this divided voltage. Using common voltage division as provided by a series of resistors such as in string
12
, and again assuming equal resistance for each element in string
12
, then for the current example the tap T
1
voltage across resistive element R
0
equals {fraction (1/7)}*V
s
.
Given the above, one skilled in the art will further appreciate that with different digital inputs, any of the transistors of DAC
10
may be enabled, and for each such transistor it will correspondingly cause an output which represents a divided voltage between 0 volts or any value incrementing up from 0 volts by {fraction (1/7)}V
s
, and up to an output equal to V
s
. However, this conclusion necessarily requires that the resistance of elements R
0
through R
6
is either identical or within some acceptable tolerance. In other words, for each one of the resistance elements that departs from this requirement of uniform resistance, the voltage across that element will depart from the value of {fraction (1/7)}V
s
. In addition, for such a resistive element, its resistance will upset the anticipated total resistance of the overall series-connected string
12
.
Given the above, it may be appreciated how a deviation in resistance value in any of elements R
0
through R
6
may provide certain drawbacks. Indeed, due to the requirement of equal resistance, one approach to avoid such drawbacks has been to form the resistive elements along a single continuous line as depicted schematically in FIG.
1
. However, for larger decoders, this may provide for too large a device. An alternative is to provide a back-and-forth resistance string, sometimes referred to as a meander, in an effort to reduce the span of the resistance string. With the meander, however, there arises complications in t
Fattaruso John W.
Mahant-Shetti Shivaling S
Brady III Wade James
Stewart Alan K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Wamsley Patrick
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