Static information storage and retrieval – Addressing – Sync/clocking
Patent
1995-06-07
1997-02-04
Nguyen, Viet Q.
Static information storage and retrieval
Addressing
Sync/clocking
36523003, G11C 700
Patent
active
056006055
ABSTRACT:
A synchronous dynamic random access memory (SDRAM) includes a memory array and is responsive to command signals and address bits. A command decoder/controller responds to selected command signals to initiate, at different times, a precharge command, an active command, and a transfer command. The command decoder/controller initiates the active command during the precharge command. Indicating circuitry responds to the precharge command to provide a precharge complete signal indicating the completion of a precharge command operation. A row address latch responds to the active command to receive and hold a value representing a row address of the memory array as indicated by the address bits provided at the time the active command is initiated, and responds to the precharge complete signal to release the row address.
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Mai Son
Micro)n Technology, Inc.
Nguyen Viet Q.
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