Data processing: speech signal processing – linguistics – language – Audio signal bandwidth compression or expansion
Reexamination Certificate
1998-04-17
2004-06-29
Chawan, Vijay (Department: 2645)
Data processing: speech signal processing, linguistics, language
Audio signal bandwidth compression or expansion
C704S201000
Reexamination Certificate
active
06757658
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to decoding and reconstruction of two channel MPEG-1 and/or multi-channel MPEG-2 audio data. More specifically, the present invention relates to decoding and reconstruction of MPEG-1 and MPEG-2 audio data using an optimized MPEG subband synthesis algorithm.
Various standards have been developed for the purpose of providing digitally encoded audio data that can be reconstructed to provide good quality audio playback. In the late 1980s, a digital audio/video reconstruction standard known as “MPEG” (for Motion Pictures Experts Group) was promulgated by the International Standards Organization (ISO). MPEG syntax provides an efficient way to represent audio and video sequences in the form of compact coded data. MPEG unambiguously defines the form of a compressed bit stream generated for digital audio/video data. Given the knowledge of the MPEG rules, one can thus create a decoder, which reconstructs an audio/video sequence from the compressed bit stream.
MPEG-2 was initiated in the early 1990s to define a syntax for higher quality audio playback for broadcast video. The MPEG-1 audio standard is described in a document entitled “Coding of Moving Pictures and Associated Audio for Digital Storage Media at up to about 1.5 MBit/s” (Part 3 Audio) 3-11171 rev 1 (1995) (hereinafter “the MPEG-1 Document”). The MPEG-2 audio standard is described in a document entitled “Generic Coding of Moving Pictures and Associated Audio Information” ISO/IEC 13818-3 (1994) (hereinafter “the MPEG-2 Document”). Both standards documents are incorporated herein by reference for all purposes. Both documents are available from ISO/IEC Case Postale 56, CH-1211, Geneva 20, Switzerland.
The MPEG-2 audio decoding algorithm requires certain steps such as decoding of bit allocation, decoding of scale factors, variable length decoding of audio samples, requantization of samples and subband synthesis. Subband synthesis further requires the steps of matrixing and windowing.
While CPU digital processing power has improved markedly in recent years, the sheer volume of encoded audio/video data that must be rapidly decompressed and played back generally requires some dedicated system hardware, beyond the CPU, for MPEG-2 decoding. CPUs like SPARC from Sun Microsystems, Inc. of Mountain View, Calif., MIPS from Silicon Graphics, Inc. of Mountain View, Calif., Pentium from Intel Corporation of Santa Clara, Calif., etc. can not, in themselves, handle MPEG-2 audio decoding simultaneously with video decoding running at a low system clock. Thus, software/firmware implementation of the MPEG-2 decoding algorithms is not yet practical for mass market consumer applications, and dedicated hardware must be employed to perform at least some MPEG-2 decoding functions.
Although the ISO/MPEG-2 and AC-3 standards do specify the form that encoded audio data must take, they do not specify either the exact sequence of steps or the hardware that must be employed in decoding the data. Thus, designers of MPEG-2 and AC-3 decoding systems are free to provide their own designs for particular applications. In fact, it is expected that each time an MPEG-2 decoder is to be designed for a new application, a designer will generate a new integrated circuit layout for the decoder.
Thus, it would be desirable to find a way to perform a functional partitioning of the MPEG-1, MPEG-2 and AC-3 audio decoding algorithms such that the partitioning allocates some of the decoding steps to be done in hardware and the remaining tasks to be done in firmware. Furthermore, in the implementation of the firmware/hardware partitioning, it is also desirable to optimize audio decoding algorithms, such as those involved during subband synthesis, to speed up decoding of MPEG audio data and reduce the memory, e.g., input RAM, size on chip.
SUMMARY OF THE INVENTION
The present invention provides a reusable hardware layout (“core”) for performing some, but not all, MPEG audio decoding functions. The functional blocks comprising this “audio core” define a unique hardware architecture which can be used with additional hardware or software for performing those MPEG audio decoding functions not performed by the audio core.
Hereinafter, except where distinctions between the two versions of the MPEG standard exist, the terms “MPEG-1” and “MPEG-2” will be used interchangeably to reference those audio decoding algorithms promulgated in the original MPEG Document as well as in the MPEG-2 Document, and any future versions of MPEG decoding.
A chip designer may use the audio core of this invention to expedite the designing of an MPEG video decoder. However, because the audio core of this invention performs only some of the MPEG decoding steps, the designer is free to design blocks optimized for the designer's purposes, to perform the remaining MPEG functions. The audio core of this invention is particularly useful for expeditiously designing “system” chips containing multiple cores on a single chip. Such cores might include, for example, the audio core of this invention, a video core, and a CPU core.
A significant benefit of an audio core derives from its availability for repeated use in many different chips for different applications. In each such chip, the audio decoding functions specified by the audio core can be employed without redesign. Thus, the audio core may be used on a first integrated circuit having a first integrated circuit design and on a second integrated circuit having a second integrated circuit design, with the first and second integrated circuit designs having at least some features not in common. If a system chip is employed, the first integrated circuit design may include a first collection of cores, while the second integrated circuit may include a second collection of cores, etc.—even though the first and second collections of cores have at least one core not in common.
The audio core design itself is preferably stored on a machine readable media such as a magnetic or optical storage unit. The information content of the core preferably includes a series of hardware layouts specifying the locations and features of various circuit elements comprising the audio core architecture. Ultimately, the audio core design is implemented as hardware on one or more chips. Thus, the audio core design exists as both an intangible description of hardware and as the actual hardware itself.
In one embodiment, the audio decoder core design specifies that at least the following MPEG functions are performed by the hardware: sub-band synthesis (or “matrixing”) and windowing. These functions are detailed in the MPEG-1 Document. In especially preferred embodiments, other MPEG-2 functions such as bit allocation decoding, scale factor decoding, variable length decoding, requantization, decoupling, rematrixing, and dynamic range compression are not performed by the audio core of this invention.
Preferably, the control logic unit specifies in which function or group of functions of the MPEG decoding process the audio core currently resides. The control logic unit includes an MPEG state machine for generating MPEG current state (also referred to as “curstate”), secondary state (also referred to as “secstate”) and loop count (also referred to as “loopcnt”), information. This information is employed by the RAM and ROM addressing logic to specify appropriate addresses for reading and writing data.
In one aspect the present invention provides a digital audio decoder. The decoder includes: (i) an audio core which defines hardware for matrixing and windowing during decoding of MPEG digital audio signals such that matrixing coefficients are multiplied by discrete modified sample values during the matrixing operation; (ii) an input RAM coupled to the audio core and configured to store the discrete modified sample values calculated outside the audio core in preparation for the matrixing operation and configured to store intermediate values calculated by the audio core during the matrixing operation that are written back to the input RAM. The mod
Kolluru Mahadev S.
Soman Satish S.
Chawan Vijay
LSI Logic Corporation
Maiorana PC Christopher P.
Opsasnick Michael N.
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