Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2000-03-27
2002-10-01
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S666000, C257S669000, C257S690000, C257S730000, C257S693000, C257S674000, C361S772000
Reexamination Certificate
active
06459147
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates to packaging of semiconductor devices in general, and in particular, to a method and apparatus for reliably connecting the die of a high power device, such as a power MOSFET device, to its associated substrate with a conductive strap.
2. Description of the Related Art
Some high power semiconductor devices are fabricated by forming a number of individual, lower power devices in a single semiconductor die, or “chip,” then “paralleling” them, i.e., connecting the individual devices together in parallel within the package of the device to define a single device capable of higher power output.
Thus, in an exemplary eight-lead, standard outline integrated circuit (“SOIC-8”) high-power, metal-oxide-semiconductor field effect transistor (“PMOSFET”) package, the sources of the individual devices, which are located on the top of the die, are connected in parallel by a thin layer of metal on the top of the die, which in turn, is internally connected to each of three leads of the package.
In prior art versions of this type of device, the sources of the individual MOSFETs were connected to the substrate of the package by a relatively large number (typically, 14) of parallel bonded wires. However, these wires contributed to a number of problems associated with this type of device, including relatively high internal thermal and electrical resistances, high parasitic source-inductance, and the formation of craters and Kirkendall voids in the die caused by the bonding of the wires.
More recently, it has been learned that most of the foregoing problems can be eliminated or reduced by replacing the large number of bonded wires from the source of the device with a single, elongated conductive strap that connects the thin layer of metal on top of the die to the source leads of the substrate. (See, e.g., U.S. Pat. No. 6,040,626 to C. Cheah, et al.; see also, Patrick Manion, “MOSFETs Break Out Of The Shackles of Wirebonding,”
Electronic Design,
Mar. 22, 1999, Vol. 47,No.6.)
However, this method of connecting the die to the substrate has also been found to have some problems associated with it. One of these relates to the differences in the respective thermal coefficients expansion (“TCE”) of the materials of the strap, die, and substrate. As a result of these differences, these parts respectively experience different amounts of expansion and contraction with changes in the temperature of the package. This relative movement of the respective parts causes large shear stresses to develop in the attachment joints between them, which are typically lap joints of conductive adhesive or solder. These shear stresses result in a degradation of the electrical connection between the strap, die, and substrate, and in particular, in an unacceptably large change, or “shift,” in the critical drain-to-source resistance of the device when on (R
DS(ON)
).
A need therefore exists for a method and apparatus for reliably connecting a semiconductor die to a substrate with a conductive strap such that the electrical connections between the parts are immune to the destructive effects of temperature-induced stresses in the connections.
SUMMARY OF THE INVENTION
This invention provides a method and apparatus for electrically connecting a semiconductor die, such as a power MOSFET, to a substrate on which the die is mounted, e.g., a lead frame, with a conductive strap, such that the connection is more resistant to the shear stresses incident upon it with changes in temperature of the device. The enhanced reliability of this connection, in turn, enhances overall device reliability and reduces semiconductor package failures due to, e.g., large changes in the device's R
DS(ON)
parameter.
The method includes the provision of a conductive strap comprising a planar cover portion having a bottom surface adapted for attachment to a top surface of the die, a down-set portion at an edge of the cover portion that transitions from the cover portion of the strap down to the substrate, and a flange portion at an edge of the down-set portion which has a bottom surface adapted for attachment to the substrate.
In one exemplary embodiment of the method, a recess is formed in the top surface of the substrate. The recess has a floor disposed below the top surface of the substrate. The bottom surface of the cover portion of the strap is attached to the top surface of the die, e.g., with a conductive adhesive, and the bottom surface of the flange portion of the strap is attached to the floor of the recess such that the recess captures the flange and prevents horizontal movement of the flange relative to the substrate with variations in device temperature.
In another embodiment of the method, first and second layers of a conductive elastomer are attached to the top surfaces of the die and the substrate, respectively. The bottom surface of the cover portion of the strap is attached to a top surface of the first layer of elastomer on the die, and the bottom surface of the flange portion of the strap is attached to a top surface of the second layer of elastomer on the substrate. This flexible connection enables the strap, die, and substrate to move freely relative to one another with large changes in device temperature while remaining reliably connected to each other.
In a third exemplary embodiment of the method, a first set of corresponding apertures is formed through respective ones of the flange portion of the strap and the substrate, and a second set of apertures is formed through the cover portion of the strap. With the corresponding apertures in the flange and the substrate in alignment with each other, the bottom surfaces of the cover and flange portions of the strap are then attached to respective ones of the top surfaces of the die and the substrate with, e.g., a conductive adhesive. The adhesive extends through the apertures in the strap and the substrate to form interlocking “keys” therein. When cured, these adhesive keys provide a much greater resistance to the shear forces induced in the connection between the strap, substrate and die by large temperature excursions in the package than do the simple lap joints of the prior art.
A better understanding of the above and other features and advantages of the present invention may be obtained from a consideration of the detailed description of its exemplary embodiments found below, particularly if such consideration is made in conjunction with the several views of the drawings appended hereto.
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Internet Website Article, Electronic Design—Mar. 22, 1999, vol. 47, No. 6- MOSFETs Break Out Of The Shackles Of Wirebonding.
File Wrapper for Provisional Patent Application No. 60/101810.
http://www.siliconix.com, “New Package Technology Yields Nearly Twofold Improvement Over Previous State-of-the-Art,” Vishay Siliconix Press Release, Dec. 9, 1998.
Aquino, Jr. Victor M.
Belmonte Ferdinand E.
Burro, Jr. Remigio V.
Crowley Sean T.
Gillett Blake A.
Amkor Technology Inc.
Parekh Nitin
Parsons James E.
Skjerven Morrill LLP
Thomas Tom
LandOfFree
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