Electrical computers and digital processing systems: interprogra – Device driver communication – Device driver configuration
Reexamination Certificate
2002-05-30
2004-09-14
Courtenay, III, St. John (Department: 2126)
Electrical computers and digital processing systems: interprogra
Device driver communication
Device driver configuration
C710S010000, C710S048000, C713S001000
Reexamination Certificate
active
06792610
ABSTRACT:
BACKGROUND
This invention relates to the field of computer systems. More particularly, a system and methods are provided for facilitating the attachment of a device driver to multiple logical communication devices.
Traditionally, a physical communication interface device, such as a Network Interface Circuit (NIC), hosts a single function for a computer system. Therefore, the operating system of the computer only needs to execute a module attachment (or detachment) procedure once for each physical device.
The use of multiple logical or physical communication devices, instead of a single device, can offer gains in communication efficiency. Although attempts have been made to operate multiple physical communication devices on a single computer board or card, it has been unknown to operate multiple logical devices on a single physical communication device in a manner requiring multiple device driver attaches (or detaches). This may be attributed to the inherent need to invoke multiple attach or detach procedures (i.e., once for each logical device), which adds complexity to the initialization of the physical device.
Also, the programming for a hardware device controlled via an FPGA (Field Programmable Gate Array), or other similar component, is often stored on a programmable read-only memory such as an EEPROM (Electrically Erasable Programmable Read Only Memory). The EEPROM contents must be re-flashed whenever the programming changes. The device's firmware may also need to be changed, along with the hardware revision, which may be an expensive process. And, updating the device's programming requires the read-only memory to be re-flashed with the new program logic—a procedure that typically cannot be performed by an average user. This makes it difficult to keep hardware devices' programming up-to-date.
SUMMARY
In one embodiment of the invention, a system and methods are provided for attaching a device driver to, or detaching a device driver from, multiple logical communication devices on a single physical device (e.g., a NIC).
To determine which physical device a logical device has been attached to, an identifier (e.g., a MAC identifier) may be read from the physical device. The identifier may be used to locate a device soft state structure for the physical device. If one does not exist, thereby indicating that the attached logical device was the first one attached, a device soft state structure is allocated and initialized.
For each attached logical device, a counter is incremented to note the number of logical devices attached to a given physical device. And, a device information pointer and instance identifier assigned to the logical device during attachment are recorded. The device information pointer may be recorded into the device soft state structure.
A selected device information pointer (e.g., for a logical device of a particular binding node name) may be used in one or more DDI (Device Dependent Interface) functions invoked after all logical devices have been attached.
During detachment of a logical device, a counter is kept of the number of logical devices detached from a given physical device. When all logical devices have been detached, allocated resources may be released, and the physical device may be reset.
In another embodiment of the invention, a system and methods are provided for delivering programming logic (e.g., an FPGA binary) to a computer system's hardware device via a device driver. The device driver may be loaded in a normal fashion, by the computer's operating system, to facilitate operation of the device.
In this embodiment, the hardware device programming instructions (e.g., an FPGA binary file) are converted into a source file for a selected programming language (e.g., C). The source file includes the contents of the binary file in a suitable data structure (e.g., an array of bytes). The source file is compiled to generate an object file, which is then linked with a device driver object file to form a device driver loadable module. When the device driver is loaded by the operating system and attached for the hardware device, the hardware device is initialized, at which time the encapsulated programming is loaded onto the device (e.g., an FPGA component of the device).
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patent: 2002/0023179 (2002-02-01), Stanley
Courtenay III St. John
Park Vaughan & Fleming LLP
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