Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
Reexamination Certificate
2005-12-27
2005-12-27
Peikari, B. James (Department: 2189)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Reexamination Certificate
active
06981128
ABSTRACT:
In a system with multiple execution units, instructions are queued to allow efficient dispatching. One load/store unit (LSU) may have a store instruction pending to a real address and a second LSU may have a load instruction pending to the same real address. An SMT system has an atomic store quad word (SQW) instruction with a data path that is only double wide and the SQW requires two cycles to complete. The SMT system requires a method to prevent between collisions in a store reorder queue (SRQ) STQ. The real address of a load word (LW) one thread is compared to the real addresses in the SRQ of the second thread. If the SQW with a real address matching the real address of the LW has not committed both of its double words, then the LW of the second thread is rejected.
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Fluhr Eric J.
Hinojosa Joaquin
Kalla Ronald N.
Ronchetti Bruce J.
Sinharoy Balaram
Frankeny Richard F.
Peikari B. James
Salys Casimer K.
Winstead Sechrest & Minick P.C.
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