Semiconductor device manufacturing: process – Making device array and selectively interconnecting
Reexamination Certificate
1999-02-10
2001-12-18
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
C438S129000, C438S962000
Reexamination Certificate
active
06331454
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a method of making an atomic-level electronic network. In particular, it relates to a circuit having a chain or array of atoms with distinct electrical characteristics related to the atomic spacing between the circuit atoms.
BACKGROUND OF THE INVENTION
In a conventional circuit network based on semiconductor device technology, functional devices made of semiconductors or insulators are connected together by relatively large metal traces designed to carry electrical signals. These structures typically require real estate on the order of tens of square micrometers, and more.
Mesoscopic structures are smaller, but still require significant real estate. To fabricate such a circuit network on a silicon substrate, diodes or transistors based on p-n junctions, or resistors made of doped semiconductors are connected by several ten nanometer wide metal lines deposited on the substrate, power is fed from a battery or an external generator, and a large ground plane is made by deposition of metal on the substrate which may be connected to the main ground. The resulting structure quickly becomes complicated and can typically require real estate on the order of hundreds of square nanometers, and more.
If the circuit network together with device elements is simply scaled down, the physical operation principle for these macroscopic devices undergoes a drastic change even at nanoscale, where the wave nature of the electrons play an important role in device operation. To further miniaturize the structures, a new device principle must be developed, adopting the atomic nature of constituent atoms forming the device.
The state of the art of the invention includes techniques for manipulating atoms such as that described in Eigler, U.S. Pat. No. 4,987,312. Eigler describes using a scanning tunneling microscope (STM) to attract atoms to an electrically charged probe tip and to move the atoms to a desired location. With regard to the substrate surface, the reference J. Lyding et al., “Nanoscale Patterning and Oxidation of H-passivated Si(100)-2×1 Surfaces with an Ultrahigh Vacuum Scanning Tunneling Microscope,” Appl. Phys. Lett. vol. 64 (1994), describes a technique for making a passivated substrate without dangling tools. The technique uses ultrahigh vacuum conditions and an ATM to H-passivate an Si surface. Such an insulated surface is one that can be used in the invention. Additionally, other references such as D. Huang et al., “Physical Mechanism of Hydrogen Deposition from a Scanning Tunneling Microscopy Tip,” Appl. Phys. A vol. 64 (1997) describe removing atoms from the passivated substrate at specified locations using an STM.
OBJECTS AND SUMMARY OF THE INVENTION
The present invention provides a method for making an atomic-level electronic network. An object of the invention is to provide a circuit that utilizes a minimum amount of real estate. A related object is to position and couple individual atoms on an insulated lattice to form an atomic chain or array. A related object is to position a plurality of chains or arrays on an insulated lattice and couple the chains or arrays together to form an atomic chain circuit network.
An insulated lattice is prepared with a plurality of lattice oriented atoms to create a substantially planar surface having a lattice arrangement. Any unsatisfied chemical bonds are terminated along the substantially planar surface by placing atoms at the site of the unsatisfied chemical bonds to terminate the unsatisfied chemical bonds and insulate the surface to form an insulated lattice platform. In one aspect of the invention, the insulator atoms are removed at predetermined locations.
Atoms to form the atomic chain are placed at predetermined locations on the insulated lattice platform to form a first atomic chain which behaves as one of a conductor, a semiconductor and an insulator. A second atomic chain is also placed at predetermined locations on the insulated lattice platform so that the second chain behaves as another of a conductor, a semiconductor and an insulator. These placements are made such that the second atomic chain is electrically coupled to the first atomic chain, and the second atomic chain behaves differently than the first atomic chain. That is, in the first chain the atoms are placed at a first separation distance to achieve the desired electrical characteristic and in the second chain the atoms are placed at a second separation distance to achieve the desired electrical characteristic, where the second separation distance is different than the first.
Other features and advantages of the invention will appear from the following description in which a preferred embodiment has been set forth in detail, in conjunction with the accompanying figures.
REFERENCES:
patent: 3988823 (1976-11-01), Hu
patent: 4122479 (1978-10-01), Sugawara et al
patent: 4589191 (1986-05-01), Green et al.
patent: 4987312 (1991-01-01), Eigler
patent: 5561300 (1996-10-01), Wada et al.
patent: 5689494 (1997-11-01), Ichikawa et al.
patent: 5981316 (1999-11-01), Yamada et al.
patent: 548905A2 (1993-06-01), None
patent: 588062A1 (1994-03-01), None
Huang et al., “Scanning Tunneling Microscope Fabrication of Atomic-Scale Memory on a Silicon Surface”,Jpn. J. Appl. Phys.33:L190-L193 (1994).
Lyding et al., “Nanoscale Patterning and Oxidation of H-passivated Si(100)-2x1 Surfaces with an Ultrahigh Vacuum Scanning Tunneling Microscope”,Appl. Phys. Lett.64(15):2010-2012 (1994).
Huang Dehuan
Takiguchi Yoshihiro
Yamada Toshishige
Yamamoto Yoshihisa
Board of Regents of the Leland Stanford Junior University
Bowers Charles
Christiansen Keith
Flehr Hohbach Test Albritton & Herbert LLP
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