Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1998-03-20
2001-08-07
Rao, Scema S. (Department: 2661)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S419000, C370S249000
Reexamination Certificate
active
06272137
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an ATM (Asynchronous Transfer Mode) transmission system, which is advantageously applied to interface portions of subsystems of an ATM switch system, for example.
2. Description of the Background Art
An ATM switch system is a considerably large system including not only an ATM switch having a CPU (Central Processing Unit), but also line termination units, channel equipment and trunk circuits. Generally, the ATM switch, line termination units, channel equipment and trunk circuits are each arranged in the form of an individual subsystem included in a separate casing. The ATM switch plays the role of a higher-order system, while the line termination units, channel equipment and trunk circuits constitute a lower-order system. The higher-order and lower-order systems are interconnected by an interface line, a maintenance information line and a timing signal line.
The interface line is provided for transferring, between the higher-order and lower-order systems, multiplexed main, or user, information and control information. More specifically, it employs the in-channel control method, in which the control information is transferred over the same transmission line as the user or main information. The maintenance information line transfers maintenance information between the higher-order and lower-order systems. The maintenance information includes a reset signal and an LED (Liquid Crystal Display) display signal sent from the higher- to lower-order system, and an interrupt signal sent from the lower- to higher-order system. A timing signal line is provided for transferring timing signals such as a clock signal and a sync signal from the higher- to lower-order system.
The higher-order system can be connected to various types of lower-order systems. For example, it can be connected to lower-order systems with different interface rates such as 622 Mbps and 155 Mbps (bit per second), for example. In the ATM switch system, in practice, the line termination unit is installed correspondingly as the lines increase, in which case the interface rates of the lower-order systems can be changed dependently upon the fact that the line termination unit is changed to a new type or one including a different capacity of lines.
The conventional ATM switch system involves the following problems. First, it is necessary to install not only the interface line for conveying the user main information and control information, but also the maintenance information line and timing line between the higher-order and lower-order systems. If both systems are located at a distance from each other, these lines are long as well. Thus, it is highly desirable that the lines other than the interface line be omitted. In practice, a lot of lines are installed between the higher-order and lower-order systems, and this presents problems of increasing connection failures and of requiring increasing area and space. The problems involved in installing the lines become more serious when applying a redundant system configuration such as a duplex system.
Second, another problem arises in that the configuration of an interface circuit between the higher-order and lower-order systems becomes complicated when the lower-order systems have different interface rates. For example, when one of the lower-order systems selects 155 Mbps as its interface rate, it is impossible to send to the one system the user main information at the interface rate of 622 Mbps. On the contrary, if it selects 622 Mbps as its interface rate, it is necessary to quadplex the 155 Mbps user main information, and dequadplex them at the receiving side.
Furthermore, although the conventional ATM switch system employs the in-channel method as mentioned above, the receiving side relinquishes the use of a processor for the user main information while receiving the maintenance information, thereby consuming time ineffectively.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an ATM transmission system capable of obviating the dedicated line for conveying the maintenance information.
Another object of the present invention is to provide an ATM transmission system which can be interconnected to other ATM transmission systems corresponding thereto, independently of their interface rates.
Still another object of the present invention is to provide an ATM transmission system capable of making use of the period of time in which the maintenance information is received to carry out a loop-back test.
A further object of the present invention is to provide an ATM transmission system for use as a component system forming a redundant system, which can acquire ATM cells sent from systems constituting a redundant system corresponding thereto with the received ATM cells aligned in phase.
According to a first aspect of the present invention, there is provided an ATM transmission system comprising: a multiplexer for multiplexing ATM cells to be sent to the ATM transmission system interconnected thereto; a maintenance information processor for generating maintenance information to be sent to the interconnected ATM transmission system; and an interface circuit for establishing interface with an interconnected ATM transmission system, wherein the interface circuit includes a data transmitter for assembling and transmitting a multiframe including an information field and an overhead portion having a multiframe sync pattern, the multiframe being assembled by inserting into the information field the ATM cells multiplexed by the multiplexer and by inserting into the overhead portion the maintenance information fed from the maintenance information processor.
The interface circuit may advantageously further comprise: a data receiver for deassembling received data including the multiframe sent from the party ATM transmission -system into the ATM cells and the maintenance information, and for providing the maintenance information processor with the maintenance information; and a demultiplexer for demultiplexing the ATM cells output from the data receiver into individual ATM cells.
The ATM transmission system may further comprise a timing generator for generating timing signals used in the ATM transmission system in response to the multiframe sync pattern in the received data.
The ATM transmission system may also further comprise a loop-back test circuit for carrying out a loop-back test of its own ATM transmission system while the overhead portion of the multiframe is being processed.
The data transmitter and the data receiver may each comprise parallel processors whose number equals a least common multiple of one or more ratios between a minimum interface rate and one or more other interface rates of the one or more interconnected ATM transmission systems, and the ATM transmission system may comprise an ATM cell transfer and acquisition circuit for providing, at the minimum interface rate, each of the parallel processors of the data transmitter with an ATM cell to be transmitted, and for acquiring, from each of the parallel processors of the data receiver, a received ATM cell sent at the minimum interface rate.
According to a second aspect of the present invention, there is provided an ATM transmission system comprising an interface circuit including a data transmitter for transmitting an ATM cell to one or more ATM transmission systems interconnected thereto, and a data receiver for receiving an ATM cell sent from the interconnected ATM transmission system, wherein the data transmitter and the data receiver each include parallel processors whose number equals a least common multiple of one or more ratios between a minimum interface rate and one or more other interface rates of the one or more interconnected ATM transmission systems; and wherein the ATM transmission system comprises an ATM cell transfer and acquisition circuit for providing, at the minimum interface rate, each of the parallel processors of the data transmitter with an ATM cell to be transmitted, and for acqui
OKI Electric Industry Co., Ltd.
Pizarro Ricardo M.
Rabin & Champagne, P.C
Rao Scema S.
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