Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1998-06-10
2002-07-02
Kizou, Hassan (Department: 2662)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S389000, C370S412000, C370S395100, C370S395200, C370S395700, C710S022000, C710S052000
Reexamination Certificate
active
06414961
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an ATM communication apparatus and, more particularly, to an ATM communication apparatus having a transmission data temporarily storing circuit for each virtual channel (to be referred to as a “VC” hereinafter).
2. Description of the Prior Art
FIG. 1
is a block diagram showing a conventional ATM communication apparatus. As shown in
FIG. 1
, the ATM cell formation/transmission section of a conventional ATM communication apparatus
1
is constituted by a transmission schedule section
8
for selecting a VC to be sent next, a cell formation/transmission control section
6
for receiving information indicating the selected VC from the transmission schedule section
8
and controlling cell transmission of the VC, a transmission parameter storage section
7
for storing information (transmission parameters) required to control cell transmission, a transmission cell formation section
9
for forming a transmission cell, and a transmission data FIFO
10
used to store the transmission cell. The ATM reception/split section of the ATM communication apparatus
1
is constituted by a reception/cell split control section
12
for breaking up and filtering a reception cell to reclaim original information, a reception data FIFO
13
for storing the payload of the reception cell after split, a host bus interface section
5
for transmitting/receiving data to/from a host system including a host CPU
2
, a host memory
3
, and a host bus
4
, and a physical layer device interface section
11
for transmitting/receiving an ATM cell to/from a physical layer device.
The ATM communication apparatus
1
is connected to the host memory
3
and the host CPU
2
through the host bus
4
. The host memory
3
stores transmission/reception payload data. For example, the host CPU
2
performs upper layer processing for a transmission/reception payload, outputs a transmission request, and manages the host memory.
FIG. 2
shows the format of the transmission parameter storage section
7
(see
FIG. 1
) in the conventional ATM communication apparatus
1
.
As shown in
FIG. 2
, with respect to one VC, the transmission parameter storage section
7
stores cell header information
31
, cell trailer information
32
, a payload storage address
33
in the host memory
3
(the host memory payload storage address
33
indicating the start address in the payload storage area in the host memory
3
), and a host memory payload capacity
34
(indicating the number of bytes of the payload stored in the continuous area starting from the payload storage address
33
). Although
FIG. 2
shows only the storage elements (storage portions) for one VC, similar storage portions exist in the transmission parameter storage section
7
for all the remaining VCs.
As shown in
FIG. 1
, the conventional ATM communication apparatus
1
includes the following signal lines: a VC number signal line
19
, a transmission parameter signal line
20
, a DMA start request signal line
21
, a payload data signal line
25
, a header/trailer data signal line
26
, and a cell data signal line
27
. Each signal line will be described in detail below with reference to FIG.
1
.
The VC number signal line
19
is used by the transmission schedule section
8
to notify the cell formation/transmission control section
6
of a VC number upon determining the VC to be sent next. The transmission parameter signal line
20
is used to exchange transmission parameters between the cell formation/transmission control section
6
and the transmission parameter storage section
7
.
The DMA start request signal line
21
is used by the cell formation/transmission control section
6
to notify the host bus interface section
5
of a DMA read address and a DMA read data length so as to start DMA transfer. The payload data signal line
25
is used to send the payload data DMA-read by the host bus interface section
5
to the transmission cell formation section
9
.
The header/trailer data signal line
26
is used to send the cell header information
31
and the cell trailer information
32
(see FIG.
2
), which are read out from the transmission parameter storage section
7
by the cell formation/transmission control section
6
through the transmission parameter signal line
20
, to the transmission cell formation section
9
. The cell data signal line
27
is used to store the transmission cell formed by the transmission cell formation section
9
in the transmission data FIFO
10
.
FIG. 3
is a flow chart showing the operation of the conventional ATM communication apparatus. The operation of the conventional ATM communication apparatus will be described with reference to
FIG. 3
, together with
FIGS. 1 and 2
.
In the conventional ATM communication apparatus, when there is a cell to be transmitted next, the transmission schedule section
8
notifies the cell formation/transmission control section
6
of a VC number for the cell to the cell formation/transmission control section
6
through the VC number signal line
19
(step S
1
“NOTIFY VC NUMBER”).
Upon reception of the notification of this VC number, the cell formation/transmission control section
6
notifies the host bus interface section
5
of the host memory payload storage address
33
stored as a DMA read address in the transmission parameter storage section
7
and 48 bytes (the value indicated by the host memory payload capacity
34
in the case of the last cell) as a DMA read data length through the DMA start request signal line
21
. The cell formation/transmission control section
6
then gives the host bus interface section
5
an instruction to DMA-read the transmission payload corresponding to one cell from the host memory
3
.
Upon reception of this instruction, the host bus interface section
5
DMA-reads 1-cell data in one bus cycle when transmission payload corresponding to one cell or more is stored in a continuous address area in the host memory
3
, and DMA read can be continuously performed in terms of the structure of the host bus
4
.
If the transmission payload is distributed in different address areas in the host memory
3
, or DMA read cannot be continuously performed in terms of the structure of the host bus
4
, 1-cell data is DMA-read in a plurality of bus cycles. The DMA-read transmission payload is sent to the transmission cell formation section
9
, in which the payload, the cell header information
31
, and the cell trailer information
32
are wrapped into a cell. This cell is stored in the transmission data FIFO
10
.
Transmission VCs are selected by the transmission schedule section
8
in units of cells, and the same VC is not necessarily selected for two cells consecutively. For this reason, DMA read of a transmission payload, transmission cell formation, and write of data in the transmission data FIFO
10
are performed in units of cells (step S
2
“TRANSFER ONE CELL”).
This operation is performed for the following reason. Assume that the transmission schedule section
8
selects a given VC as a transmission VC. In this case, if the payload data of two or more cells corresponding to the VC is stored in the transmission data FIFO
10
, the transmission sequence is disturbed when the transmission schedule section
8
selects another VC as the next transmission VC.
The transmission cell stored in the transmission data FIFO
10
is sent to a physical layer device through the physical layer device interface section
11
(step S
3
“TRANSMIT ONE CELL”).
The following problems (first and second problems) are posed in the above ATM communication apparatus (to be referred to as the prior art hereinafter).
The first problem is poor transfer efficiency on the host bus (see reference numeral
4
in FIG.
1
).
This is because, in the prior art, DMA read of transmission data in unit of cells produces an overhead associated with arbitration for bus access and the like for each DMA read. Assume that the ATM communication apparatus master-reads payload data from the host memory through a PCI bus in
Foley & Lardner
Kizou Hassan
LandOfFree
ATM switching with virtual circuit FIFO buffers does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with ATM switching with virtual circuit FIFO buffers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and ATM switching with virtual circuit FIFO buffers will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2867023