Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1997-11-17
2001-03-06
Marcelo, Melvin (Department: 2663)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S412000
Reexamination Certificate
active
06198742
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to an ATM (Asynchronous Transfer Mode) switching system and, more particularly, to an LSI-based line interface of an ATM switch, for inserting a management cell.
FIG. 6
is a diagram illustrating a construction of a line interface of a prior art ATM switch.
As shown in
FIG. 6
, a line interface
110
constructed of one LSI and provided between a physical layer
120
and an ATM cell switch
130
. The line interface
110
includes an input cell processing portion
111
, a first template
113
, an output cell processing portion
112
and a second template
114
. Herein, a cell flow from the physical layer
120
toward the ATM switch
130
is called a “input cell flow”. A cell flow from the ATM switch
130
toward the physical layer
120
is termed an “output cell flow”. The input cell processing portion
111
and the output cell processing portion
112
individually execute a normal ATM process and an insertion/divergence process etc with respect to the input cell flow and the output cell flow as well.
Generally, the ATM switching system requires such a function that network management cells such as an OAM (Operation And Maintenance) cell and an RM (Resource Management) cell etc are generated by a switch node and inserted into the cell flow. These inserted cells have a predetermined format and are therefore easy to generated on condition that they hold a cell data template.
The line interface
110
constituting the conventional ATM switch holds the cell template (format) through a RAM or a ROM within the LSI in order to correspond to the insertion of the cells such as the OAM cells and the RM cells having the fixed format. These are the first template
113
and the second template
114
. Then, the input cell processing portion
111
and the output cell processing portion
112
execute the process of inserting the management cells into the input cell flow or the output cell flow on the basis of the first template
113
or the second template
114
as the necessity arises.
The line interface LSI constituting the prior art ATM switch, however, holds those templates through the RAM or the ROM within the LSI in order to correspond to the insertion of the cells such as the OAM cells and the RAM cells having the fixed format, which leads to an increase in size of the line interface LSI. Further, when using the ROM, the fixed format of the template is made unchangeable enough to produce such a possibility that the format might lose a degree of freedom to change corresponding to the system.
Moreover, when inserting the network management cells such as the OAM cells and the RM cells, in the conventional ATM switch, a fixed type sequencer executes a series of processes ranging from a judgement of a necessity for inserting the management cells, a generation of the management cells to the insertions into the input/output cell flows, and it was therefore impossible to flexibly deal with alterations in processing contents that correspond to the systems and alterations due to changes in specifications of communications protocol.
Further, a system for incorporating a microcode sequencer into the line interface LSI in the line interface module has been proposed as a system for coping with the problem concerning the flexibility described above. This system is, however, based on the premise that the series of processes ranging from the judgement of the necessity for inserting the management cells to the insertion into the cell flow are to be executed within a 1-cell processing time by two microcode sequencers for respectively managing the I/O cell flows. Therefore, an excessive performance has been demanded of a processing throughput of the sequencer.
SUMMARY OF THE INVENTION
It is a first object of the present invention to downsize a line interface device by retaining a data template in a fixed format of a network management cell on a cell buffer, and simultaneously easily change a specified value of the template.
It is a second object of the present invention to provide a contrivance capable of flexibly dealing with a change in a processing content itself, in which each of processing devices for processing input/output cell flows is constructed of a microcode sequencer, and processes relative to generation and insertion of the management cells are thereby controlled based on firmware.
It is a third object of the present invention to reduce burdens upon input/output cell processing devices by providing an independent processing device for executing a process of inserting the management cell in addition to the input/output cell processing devices, and to converge the processes relative to the template of the management cell at one place.
It is a fourth object of the present invention to provide a contrivance capable of flexibly dealing with a change in processing content itself, in which each of an input cell processing portion, an output cell processing portion and a management cell generation/insertion processing portion is constructed of a microcode sequencer, and respective processes are thereby controlled based on firmware.
It is a fifth object of the present invention to enable a management cell generation/insertion processing portion to operate without depending on timing at which process requests are issued from an input cell processing portion and an output cell processing portion by transmitting the process request issued between the input and output cell processing portions and the management cell generation/insertion processing portion via a FIFO portion, and to reduce a throughput of the management cell generation/insertion processing portion down to substantially an average throughput of a request issuance.
It is a sixth object of the present invention to downsize a line interface LSI by use of a buffer memory classified as an existing memory, and decrease costs on the side of users.
The present invention is characterized such that a cell inserting process is executed by an LSI constituting the line interface of an ATM switch, and, on the other hand, a template of cell data subjected to a cell inserting process is held within an external memory (cell buffer) managed by the line interface LSI in order to accumulate input/output cell flows.
Further, two internal processors for managing the input/output cell flows detect a necessity for inserting the cells in order to implement the cell insertion. A third internal processor, which executes a communications protocol process relative to an OAM cell and an RM cell, generates the insertion cells. On this occasion, what is characterized is an efficient preparation for the insertion cells with reference to the cell data template.
Moreover, a system for transmitting an indication of the cell insertion to the third processor from the two internal processors for managing the input/output cell flows, is characterized by directly transmitting a process request from the two processors to a process request FIFO portion for managing a processing content of the third processor.
REFERENCES:
patent: 5402416 (1995-03-01), Cieslak et al.
patent: 5724354 (1998-03-01), Tremel et al.
patent: 5920558 (1999-07-01), Saito et al.
Fujisawa Toshio
Hasegawa Jun
Saito Toshitada
Hogan & Hartson LLP.
Kabushiki Kaisha Toshiba
Marcelo Melvin
Nguyen Phuongchau Ba
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