Multiplex communications – Wide area network – Packet switching
Patent
1993-05-20
1995-10-17
Olms, Douglas W.
Multiplex communications
Wide area network
Packet switching
370 941, H04J 324, H04L 1256
Patent
active
054597242
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The present invention relates to an Asynchronous Transfer Mode (ATM) switching arrangement having a flexible design structure both as regards size and rate and capable of broadcast transmission. It is capable of being made more compact and cheaper as technology improves without the necessity of making changes in logical operation. It is basically synchronous in operation and the internal bandwidth is only twice the switched bandwidth.
BRIEF DESCRIPTION OF THE DRAWING
The present invention will now be described, by way of example, with reference to the accompanying drawings, in which:
FIG. 1 shows a diagrammatic view of a known ATM switch;
FIG. 2 shows a conceptual view of an ATM switch according to the present invention;
FIG. 3 shows a diagrammatic view of an ATM switch according to the present invention;
FIG. 4 shows the use of forward transfer stores for multicast operation;
FIG. 5 shows the basic sequence of port operation for point to multipoint connections;
FIG. 6 shows a diagrammatic view of a data plane of a switch according to the present invention;
FIG. 7 shows the logical structural of an ATM switch according to the present invention;
FIG. 8 shows a diagrammatic view of the core of the switch of FIG. 7;
FIG. 9 shows a diagrammatic representation of the physical structure of a switch using 165M technology;
FIGS. 1Oa, 10b and 10c show examples of switch configurations for use in the switch of FIG. 7;
FIG. 11 shows a diagrammatic view of a further switch configuration;
FIG. 12 shows a diagrammatic view of a control plane for an Enormous switch according to the present invention;
FIG. 13 shows a schematic view of a central control for a switch as shown in FIG. 7;
FIG. 14 shows a possible configuration for a Rotator ASIC;
FIG. 15 shows a possible configuration for a Central Data Switch ASIC;
FIG. 16 shows a possible configuration for a Central Control Memory Manager ASIC;
FIG. 17 shows a possible configuration for a Central Port Controller ASIC;
FIG. 18 shows a schematic view of the operation of a Timeslot Manager ASIC;
FIG. 19 shows a block diagram of the Peripheral Port support ASIC;
FIG. 20 shows a possible configuration for an RX Port ASIC;
FIG. 21 shows a possible configuration for a TX Port ASIC;
FIGS. 22a and 22b show diagramatically a forward transfer store.
SUMMARY OF THE INVENTION
The following three definitions are used in this specification: one output port. and goes to many of the output ports (possibly all). goes to a maximum of three other ports.
First the functions of ATM switch fabrics are considered (in Section 2). Using fast synchronus circuit switching techniques, in key areas of the design it shows how high performance switches may be implemented. The performance of this switch is compared with that of an "ideal" ATM switch, to give a true measure of the high performance obtained. This form of switch is very easy to control, manage, and maintain due to the predictive nature of its internal operation.
A three stage structure is used for the switch comprising of: input queuing, central routing and output queuing this is a Time-Space-Time structure. Dynamic variable routing can be used across the routing stage due to the fact that a fixed delay is exhibited for all paths supporting a particular virtual connection. Use is made of the time domain to provide diversity of central routing.
The switch described has similarities to the switches described in U.K. patent applications Nos. GB 2224417A, GB 9019340.0, and GB 9103759.8 and in paper A6.1 "Synchronous ATM Switching Fabrics" given at ISS90 and "Advances in Digital Switching Architecture" given at 2nd IEE Conference on Telecommunications and imported herein by reference.
According to the present invention there is provided an ATM telecommunications switch comprising a plurality of parallel data switching planes and a parallel control plane, each plane having an equal number of input ports and output ports and a central switching unit to switch each input port to any output port, further comprising m
REFERENCES:
patent: 5202885 (1993-04-01), Schrodi et al.
patent: 5222063 (1993-06-01), Foglar et al.
patent: 5228031 (1993-07-01), Mertelmeier et al.
patent: 5253251 (1993-10-01), Aramaki
Advances in Digital Circuit Switching Architecture, T. S. Maddern et al. Undated.
Patent Abstracts of Japan, Pub. No. JP55140347, Pub. Date Nov. 1, 1980.
Proceedings of IEEE, vol. 78, No. 1, Jan. 1990. pp. 133-167 F. A. Tobagi. "Fast packet switch architectures for broadband Integrated Services Digital Networks".
Computer Communications, vol. 12, No. 6, Dec. 1989, pp. 349-358 M. Listanti et al. "Switching Structures for ATM".
International Switching Symposium vol. IV pp. 109-114. R, J. Proctor et al. "Synchronous ATM Switching Fabrics".
Jeffrey Mark T.
Maddern Thomas S.
Proctor Richard J.
GPT Limited
Ngo Rickey G.
Olms Douglas W.
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