Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1998-10-30
2001-08-28
Ton, Dang (Department: 2732)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
Reexamination Certificate
active
06282199
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an asynchronous transfer mode (ATM) system; and, more particularly, to an ATM switch system for efficiently providing a divided nibble clock pulse to be used in converting ATM cells into data with a preset bit length at a device in the system.
BACKGROUND OF THE INVENTION
In an asynchronous transfer mode (ATM) switch system, an ATM node connects an ATM network to another ATM network or to ATM subscribers. The ATM switch system handles information of ATM cells, each cell having a predetermined fixed bit length and being transferred asynchronously in the ATM network.
Conventionally, the ATM switch system incorporates therein a switch device, a subscriber access block, a trunk access device, a plurality of link devices, and a device controller. The switch device exchanges the ATM cells between, e.g., two link devices. Each of the link devices performs serial/parallel conversion to transfer ATM cells between the switch device and the subscriber access device or the trunk access device, receives the ATM cells serially from the access device and provides the switch device with the received ATM cells parallel, e.g., with 4-bit data width (nibble-by-nibble), and a cell synchronization signal, e.g., a nibble cell synchronization (NCS) signal, activated during a first nibble transfer of each ATM cell.
Each of the link devices also monitors cell synchronization and applies a synchronization loss signal to the device controller. Specifically, each of the link devices checks whether or not the ATM cell applied thereto is synchronized with the NCS signal and activates the synchronization loss signal when the ATM cell is not synchronized with the NCS signal. For example, if one of the link devices is not connected physically to the subscriber access device/trunk access device, or is not synchronized with the access device/trunk access device, or has a heavy fault therein, said one of the link devices activates the corresponding synchronization loss signal.
The device controller checks periodically, e.g., at every 1 millisecond, the status of the synchronization loss signal applied from each of the link devices. When the device controller detects the activation of the synchronization loss signal from said one of the link devices, the device controller applies a malfunction signal to the switch device. In response to the malfunction signal, the switch device issues a control signal to said one of the link devices to replace same with a substitution device of the link devices.
Each of the devices incorporated in the ATM switch system, on the other hand, includes a clock generation unit which generates a nibble clock pulse (NCP) and two or more NCS signals. Said two or more NCS signals have different clock phases, wherein, for example, there are phase differences of 2N or 2N+1 periods of the NCP between them, N being a positive integer. As is known in the art, the NCP is used to process each of the ATM cells synchronously, whereas each NCS is used for each device to inform a counterpart device of the beginning point of time of the ATM cells. One of the two or more NCS signals is used for said each device to transfer ATM cells to a counterpart device synchronously; and the remainder of the two or more NCS signals are used for said each device to receive ATM cells transmitted from the counterpart device synchronously. The number of the one or more NCS signals corresponds to that of the devices in the ATM switch system.
Each device further includes a clock pulse division unit which produces a divided NCP to be used in converting the ATM cells of unit of nibble into data of unit of a preset bit length, e.g., byte, wherein the divided NCP is obtained by dividing the NCP by two. Based on the divided NCP, said each device converts the ATM cells applied thereto into data of unit of byte and then processes the data converted.
Since, however, the divided NCP is obtained by using only the NCP without taking into account the two or more NCS signals, there may exist phase discrepancies between each of the NCS signals and the divided NCP. Accordingly, in case a device in the ATM switch system alternately employs the two or more NCS signals, ATM cells being processed in the device may be lost or corrupted, lowering the reliability of data in the ATM switch system.
SUMMARY OF THE INVENTION
It is, therefore, a primary object of the present invention to provide an ATM switch system capable of improving the reliability of data being processed in the system by employing an efficient clock pulse division technique.
In accordance with the present invention, there is provided an asynchronous transfer mode (ATM) switch system for generating a divided clock pulse to be used in converting ATM cells of unit of a first predetermined data length into data of unit of a second predetermined data length, the system comprising:
means for generating a clock pulse and a plurality of cell synchronization signals with different phases;
means for issuing a selection control signal and a reset signal based on the clock pulse and the cell synchronization signals;
means, in response to the selection control signal, for selecting one of the cell synchronization signals;
means for generating an initialization control signal based on the selected cell synchronization signal and the reset signal; and
means, in response to the initialization control signal, for dividing the clock pulse by M based on a previous divided clock pulse, M being a positive integer larger than 1, to thereby generate the divided clock pulse.
REFERENCES:
patent: 5384774 (1995-01-01), Martin et al.
Bacon & Thomas PLLC
Mercury Corporation
Sam Phirin
Ton Dang
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