ATM switch system capable of preventing ATM cells with...

Details ATM switch system capable of preventing ATM cells with... ATM switch system capable of preventing ATM cells with...

1998-10-02

2002-04-16

Chin, Wellington (Department: 2664)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S413000

Reexamination Certificate

active

06373843

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an asynchronous transfer mode (ATM) system; and, more particularly, to an ATM switch system capable of preventing ATM cells with synchronization loss from being applied to a switch block thereof.
BACKGROUND OF THE INVENTION
An asynchronous transfer mode (ATM) switch system constructs an ATM node for connecting an ATM network to another ATM network or connecting ATM subscribers to the ATM network. The ATM switch system handles information divided into ATM cells having a fixed length and being transferred asynchronously in an ATM network. Referring to
FIG. 1
, a conventional ATM switch system
1
comprises a switch block
2
, a processor block
3
and a plurality of link blocks, e.g., blocks
4
and
5
shown in FIG.
1
.
The switch block
2
exchanges the ATM cells between two link blocks
4
and
5
.
Each of the link blocks
4
and
5
performs serial/parallel conversion to transfer ATM cells between the switch block
2
and a subscriber access block (not shown) or a trunk access block (not shown). Each of the link blocks
4
and
5
receives the ATM cells serially from the access block (not shown), each cell having a predetermined length. And each of the link blocks
4
and
5
applies the received ATM cells parallel, e.g., with 4-bit data width (nibble-by-nibble), to the switch block
2
and a cell synchronization signal, e.g., a nibble cell synchronization (NCS) signal, activated during a first nibble transfer of each ATM cell.
Each of the link blocks
4
and
5
monitors cell synchronization and applies a synchronization loss (SL) signal to the processor block
3
. That is, each of the link blocks
4
and
5
checks whether or not the ATM cell applied thereto is synchronized with the NCS signal and activates the SL signal when the ATM cell is not synchronized with the NCS signal. For example, if one of the link blocks
4
and
5
is not connected physically to the subscriber access block/trunk access block (not shown), or is not synchronized with the access block/trunk access block (not shown), or has a heavy fault therein, said one of the link blocks
4
and
5
activates the corresponding SL signal.
The processor block
3
checks periodically, e.g., at every 1 millisecond, the status of the SL signal applied from each of the link blocks
4
and
5
. When the processor block
3
detects the activation of the SL signal from said one of the link blocks
4
and
5
, the processor block
3
applies an isolation control signal to the switch block
2
. The switch block
2
applies an isolation signal to said one of the link blocks
4
and
5
to isolate it from the switch block
2
. And also, the switch block
2
controls a substitution block of the link blocks
4
and
5
to succeed said one of the link blocks
4
and
5
.
When the switch block
2
applies the isolation signal to said one of the link blocks
4
and
5
, the latter stops transferring the ATM cell to the switch block
2
.
However, said one of the link blocks
4
and
5
is not isolated immediately because the processor block
3
performs status checking periodically and performs isolation via the switch block
2
. Therefore, a number of the ATM cells with the synchronization loss are transferred to the switch block
2
before the corresponding block is isolated from the switch block
2
.
SUMMARY OF THE INVENTION
It is, therefore, a primary object of the present invention to provide an ATM system capable of preventing ATM cells with synchronization loss from being applied to a switch block thereof.
In accordance with the present invention, there is provided an ATM switch system having a switch for exchanging an ATM cell between one of the inputs thereto and one of the outputs therefrom, comprising:
a plurality of linking blocks, each block coupled with the switch for applying the ATM cell to a selected one of the inputs to the switch, wherein each of the linking blocks checks whether or not the ATM cell is synchronized with a cell synchronization signal and activates a synchronization loss (SL) signal when the ATM cell is not synchronized with the cell synchronization signal;
an administrating block coupled with each of the linking blocks for checking whether or not the SL signal for each of the linking blocks is activated for a predetermined number of successive ATM cells and for isolating a selected one of the linking blocks, at which the SL signal is activated for the predetermined number of successive ATM cells, from the switch, wherein the isolated selected linking block stops applying the ATM cells to the switch; and
a processor coupled with the switch and the administrating block for controlling the switch to receive the ATM cell from a substitution block from the remaining linking blocks when the selected linking block is isolated.


REFERENCES:
patent: 5309432 (1994-05-01), Kanakia
patent: 5394394 (1995-02-01), Crowther et al.
patent: 5680425 (1997-10-01), Morzano
Brown et al, An IRAM-based Architecture for a Single-Chip ATM Switch, Harvard University, pp. 1-32, 1997.

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