Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1999-11-09
2003-05-06
Rao, Seema S. (Department: 2666)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S416000, C711S100000
Reexamination Certificate
active
06560232
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an ATM switch, and more specifically, to an input buffer type ATM switch capable of avoiding a collision between a plurality of cells, which is caused at an output port.
2. Description of the Related Art
An ATM (Asynchronous Transfer Mode) switch determines an output port which is an output destination of an ATM cell (hereafter, merely referred to as a cell) inputted from an input port. That is, the ATM switch stores a cell inputted from the input port in a buffer, and switches the stored cell, and then outputs the switched cell from a predetermined output port. The ATM switch is classified into an input buffer type, a common buffer type, an output buffer type and a cross point buffer type, depending on a buffer configuration method.
FIG. 1
shows an example of a conventional input buffer type ATM switch having four inputs and four outputs. This ATM switch
201
is composed of a first input buffer
202
1
having a first input port
203
1
, a second input buffer
202
2
having a second input port port
203
3
, a fourth input buffer
202
4
having a fourth input port
203
4
, a self-routing section
205
and a collision detector
207
.
The first input buffer
202
1
to the fourth input buffer
202
4
temporarily store therein the cells inputted from the first input port
203
1
to the fourth input port
203
4
, respectively. The cells stored in the first to fourth input buffers
202
1
to
202
4
are sent to the self-routing section
205
.
The self-routing section
205
is provided with a first output port
206
1
, a second output port
206
2
, a third output port
206
3
and a fourth output port
206
4
. This self-routing section
205
carries out a routing operation to output the cells sent from the first to fourth input buffers
202
1
to
202
4
to any of the first to fourth output ports
206
1
to
206
4
.
The collision detector
207
detects whether or not a cell from a certain input buffer collides with a cell from another input buffers at any of the first to fourth output ports
206
1
to
206
4
. In detail, the collision detector
207
receives routing information of the cells from the first to fourth input buffers
202
1
to
202
4
, and then judges whether or not the collision between the cells is caused at least one of the first to fourth output ports
206
1
to
206
4
. Then, the collision detector
207
sends back the judged result to the first to fourth input buffers
202
1
to
202
4
.
When each of the first to fourth input buffers
202
1
to
202
4
judges that the collision is not caused at any of the first to fourth output ports
206
1
to
206
4
by referring to this judged result, it sends the stored cell while maintaining its original state to the self-routing section
205
. On the other hand, when each of the first to fourth input buffers
202
1
to
202
4
judges that the collision occurs at any of the first to fourth output ports
206
1
to
206
4
, it determines a victory or a defeat among the collision cells. Then, the victory cell is sent while maintaining its original state to the self-routing section
205
without a delay. The defeat cell is temporally stored in the input buffer. The input buffer in which the defeat cell is stored sends the routing information to the collision detector
207
when the defeat cell is sent out. Then, the input buffer judges whether or not the collision is caused at any of the first to fourth output ports
206
1
to
206
4
again.
FIG. 2
shows another example of a conventional input buffer type ATM switch having four inputs and four outputs. This ATM switch
210
is composed of a first input buffer
212
1
having a first input port
213
1
, a second input buffer
212
2
having a second input port
213
2
, a third input buffer
212
3
having a third input port
213
3
, a fourth input buffer
212
4
having a fourth input port
213
4
, a self-routing section
215
and a collision detector
217
.
The first to fourth input buffers
212
1
to
212
4
store therein the cells inputted from the first to fourth input ports
213
1
to
213
4
, respectively. The routing information of the cells stored in the respective first to fourth input buffers
212
1
to
212
4
are sent to the collision detector
217
which is located between the self-routing section
215
and these first to fourth input buffers
212
1
to
212
4
. The self-routing section
215
is provided with a first output port
216
1
, a second output port
216
2
, a third output port
216
3
and a fourth output port
216
4
.
The collision detector
217
detects whether or not a cell from a certain input buffer collides with a cell from another input buffers at any of the first to fourth output ports
216
1
to
216
4
in accordance with routing information of the cells. Then, the cell which is judged not to collide with the other cells at any of the first to fourth output ports
216
1
to
216
4
is sent through the collision detector
217
to the self-routing section
215
.
The self-routing section
215
distributes the cell to any of the first to fourth output ports
216
1
to
216
4
, in accordance with the routing information. On the other hand, if such a judgement is made that the collision occurs at any of the first to fourth output ports
216
1
to
216
4
, the victory and the defeat are determined between the collision cells. Then, the victory cell is sent while maintaining its original state through the collision detector
217
to the self-routing section
215
without a delay. The defeat cell is temporally stored in the input buffer. The input buffer in which the defeat cell is stored sends the routing information to the collision detector
217
when this defeat cell is sent out, and judges whether or not the collision is occurred at any of the first to fourth output ports
216
1
to
216
4
.
In the ATM switch, when any adjustment is not carried out, such a state may be caused that a plurality of cells inputted from a plurality of input ports is sent to one output port at the same time. To avoid the above state, the ATM switch is provided with the input buffers and the collision detector, as shown in
FIGS. 1 and 2
, and the collision detector investigates whether or not the collision is caused between the cells in advance. If the occurrence of the collision is detected, one of the plurality of collision cells (the victory cell) is outputted to the output port, and the remaining cells (the defeat cells) are temporally waited in the input buffer. After that, the judgment whether or not the collision is caused is repeatedly performed. The cells, which won in the collisions, are outputted from the output port, one by one.
The occurrence of the collision between the cells may bring about such a situation that when a frame is assembled from the cell, the cell is lost or the cell is arraigned in an erroneous order. In order to avoid such a situation, it is important to determine a buffer capacity in each of the buffer configuration methods. However, a diversification of a communication method in recent years makes an estimate of the buffer capacity required by each of the buffer configuration methods difficult. So, the most of the ATM switches, which are presently sold in a market, are equipped with a large capacity of a buffer at a former stage of an input section, in addition to a buffer having a capacity required by each of the buffer configuration method, in order to cope with an unexpectedly burst traffic. According to this configuration, although a cell loss characteristic can be improved, hardware thereof becomes enormous. Thus, this is contrary to the request of the simplicity of the buffer configuration.
So, a technique is developed which uses an FIFO (First In—First Out) memory and a selection circuit to thereby simplify the buffer configuration simpler and also speed up the entire ATM switches and the input buffer. For example, Japanese Laid Open Patent Application (JP-A-Heisei 5-292116) discloses “CONTROL CIRCUIT FOR INPUT BUFFER TYPE ATM SWITCH”. This control circui
Jagannathan Melanie
NEC Corporation
Rao Seema S.
LandOfFree
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