ATM switch

Details ATM switch ATM switch

2000-03-06

2002-12-31

Chin, Wellington (Department: 2664)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S395410

Reexamination Certificate

active

06501757

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a versatile ATM cell switch element ASIC having provisions for expandability of number of buffers used to store the cells, and for efficient implementation of internal queues by utilizing the slicing concept. Further the ATM ASIC of the present invention possesses an advantage of configurability of the speeds of input streams while maintaining the total throughput.
BACKGROUND OF THE INVENTION
The ACE ASIC of the present invention is capable of operating at a standard basic link speed, multiples of standard basic link speed and/or combinations thereof while maintaining a constant throughput, without requiring change in the architecture of the switching element. The expandability of the number of buffers, i.e., buffer expansion, used to store the cells is enabled by equipping more devices.
The broadband integrated services digital network (BISDN) which provides for high speed and high density data communications while integrating voice, video and data over a single speed network, are being commercially exploited. CCITT standards recommend implementation of asynchronous transfer mode (ATM) packet switching in BISDN applications which utilizes packet switches for routing information in fixed size data packets called cells between a plurality of inputs and outputs.
Prior art ATM packet switches generally include single stage switches e.g., knock out switch and multistage switches, e.g., starlight switch, each being manifest with their own problems. The knock out switch architecture suffers from several limitations that limit its use in broadband applications. It requires a large number of packet filters and large concentrator which significantly increases the cost and complexity of the packet switches, especially for networks with a great number of inputs and outputs. Another limitation of the knock out switch architecture is that it utilizes a large number of memory buffers for output buffering and requires memory speed-up to accept multiple packets simultaneously at each output port. Additionally knock out type switches do not include the means for sorting data packets for priority and therefore require additional hardware for this function. Finally the implementation of multicasting in a knock out switch requires each output port to first accept all multicast packets and then to reject those that do not belong to it. This also requires additional hardware including large memory buffers to store all the multicast addresses and additional logic to determine whether to accept or reject a multicast packets at the output port.
Similarly starlight switch also suffers from several limitations that limit its utility in broadband applications. For example, to achieve low packet loss, the starlight architecture requires a large sorter and trap network, thereby increasing the number of sorting and switching elements several fold. Additionally the starlight architecture is not modular or expandable in small increments and requires a separate copy network thus increasing the cost of the switch.
Another type of the prior art packet switch is shared buffer switch which finds limited use because it must be operated at a much higher speed for writing all the packets in one clock cycle, thus often introducing head of line blocking. Additionally these switches do not offer a priority mechanism and are not modular.
U.S. Pat. No. 6,011,779 relates to a switch queuing system for transferring cells from a plurality of input channels to a plurality of output channels where the switching system claims to minimize the cell loss for bursty traffic while delay for time-critical data is also avoided. The ATM switch drops cell on a per connection basis, rather than on cell priority level. The sender(s) of the congestion causing data is penalized, rather then other users of the ATM switch.
U.S. Pat. No. 6,009,078 relates to an ATM switch capable of favorably controlling traffic congestion. The ATM switch structure is capable of detecting the traffic congestion all over the ATM switch device by the total queue monitoring buffer and to assure delivery of the output cells equal to the minimum guaranteed value. Each minimum guaranteed value may be determined for each service class and a multicast cell.
U.S. Pat. No. 5,875,190, relates to an ATM switching system, for distributing and concentrating input data packets that is comprised of a distribution section and a concentration section comprising N-priority concentration sorters each having N inputs and L outputs, L being less than N. The sorters comprise means for ordering data packets according to priority information and for transferring only the L data packets according to priority information and for transferring only the L data packets from N inputs which have the highest relative priorities. A multiplicity of the switching arrangements can be interconnected to provide an expanded switching arrangement.
U.S. Pat. No. 5,271,004 relate to an asynchronous transfer mode switching arrangement providing broadcast transmission which includes a serial to parallel converter arranged to receive input packets of data which include routing information, in serial form and convert the packets of data to parallel form. A first random access memory is provided in which each packet of data is entered at an addressed location into the memory, and the address is entered in a respective first-in first-out output queue at the tail.
U.S. Pat. No. 5,859,846 defines a fully interconnected ATM switching apparatus comprising a plurality of line interface circuits, each of the line interface circuits including an input port driver for extracting an SDH transmission frame containing cell data with a fixed length and a connection identifier from an input signal, appending a routing tag to the extracted SDH transmission frame through an input dedicated bus and an output port driver for receiving a cell stream from an output dedicated bus, removing the routing tag from the received cell stream, translating a channel identifier in the connection identifier and transferring the resultant SDH transmission frame to an adjacent node, a system clock distributor for generating a clock signal, an initialization controller for controlling a system and restart operations, a switch maintenance controller for performing a switch maintenance control operation in response to a network managing cell, a switch call processing controller for performing a call processing operation, a switch module controller for controlling a switching operation, and a plurality of switch output multiplexers for switching cells from the input port drivers to the output port drivers under the control of the switch module controller.
U.S. Pat. No. 6,009,100 relates to an asynchronous transfer mode switching network can be made to look like a synchronous tandem switch to end offices connected to the network by establishing a permanent virtual path through the network that carries information between the end offices. Individual channels to be switched are assigned ATM VCI addresses at both ends that correspond to the time slot to the time slot channel being sent and a time slot channel being received.
U.S. Pat. 5,636,210 claims to employ an inexpensive and efficient architecture that is modular and expandable. This patent incorporates priority sorting and improved multicasting while requiring a minimum amount of memory buffers. This patent discloses an ATM packet switch for routing data packets between a plurality of input and output devices. It claims to provide a high degree of modularity by allowing expansion of the switch to handle applications having less than eight input and output devices to applications having 2
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input and output devices. This patent broadly classifies the single stage switch, two stage switch and three stage asynchronous packet switches each being capable of routing packets between different number of input and out devices. The single stage packet switching is used for routing data packets between eight or less input and output devices by us

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