ATM switch

Details ATM switch ATM switch

1998-03-18

2004-04-20

Nguyen, Chau (Department: 2663)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S395100, C370S395300

Reexamination Certificate

active

06724760

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to an ATM (Asynchronous Transfer Mode) switch, and more particularly to an ATM switch of compact size.
2. Description of the Related Art
The ATM switch technique is the core of the broadband integrated services digital networks (B-ISDN) which has recently been researched and developed. The ATM switch switches ATM cells each having a fixed length in accordance with header information.
The connection services of the ATM switch are mainly grouped into a point-to-point connection and a multicast connection (point-to-multipoint connection). The point-to-point connection provides services so that a connection between two terminals is made via a switch and a communication takes place between these terminals only. The normal telephone services are implemented by the point-to-point connection.
The multicast connection provides services so that a connection is made between one information sending terminal and a plurality of information receiving terminals via a switch. An example of the multicast connection is a CATV service (video on demand) via a network.
There are two types of the conventional multicast connection, namely, a multistage self routing (MSSR) switch having a cell copy function, and a distribution trunk (DTRK) system.
FIG. 1
is a block diagram of a system using the MSSR switch. An MSSR switch
10
includes input highways
11
and
12
, output highways
13
and
14
, and SRMs (self routing modules)
15
,
16
,
17
and
18
arranged at crosspoints of the input and output highways. The MSSR switch shown in
FIG. 1
is a two-input, two-output structure.
FIG. 2
shows a four-input, four-output MSSR switch. The modules SRM located at the crosspoints has a crosspoint ID (CPID) assigned to a respective column of the matrix formation. For example, the crosspoint ID of the modules SRM located at the four crosspoints which cross output highway #1 is
1
, and the crosspoint ID of the modules SRM located at the four crosspoints which cross output highway #2 is
2
. Similarly, the crosspoint ID of the modules SRM located at the four crosspoints which cross output highway #3 is
3
, and the crosspoint ID of the modules SRM located at the four crosspoints which cross output highway #4 is
4
.
The ATM cells transferred over the input highways #1-#4have a tag added to a header, as shown in parts (A) and (B) of FIG.
3
. As shown in part (C) of
FIG. 3
, the tag includes ID numbers CP
1
, CP
2
, CP
3
and CP
4
. When the module SRM indicated by the crosspoint ID of
1
is instructed to latch the ATM cells, CP
1
is equal to 1. When the module SRM indicated by the crosspoint ID of
1
is instructed not to latch the ATM cells, CP
1
is equal to 0. When the CP
2
, CP
3
and CP
4
are equal to 1, the modules SRM respectively indicated by the crosspoint IDs CPID
2
, CPID
3
and CPID
4
are instructed to latch the ATM cells. When the CP
2
, CP
3
and CP
4
are equal to 0, the modules SRM respectively indicated by the crosspoint IDs CPID
2
, CPID
3
and CPID
4
are instructed not to latch the ATM cells.
If an ATM cell A transferred over the input highway #3 has the tag in which CP
2
=CP
3
=1 and CP
1
=CP
4
=0, the ATM cell A is latched in the modules SRM
32
and SRM
33
shown in
FIG. 2
, so that the identical ATM cells A are output to the output highways #2 and #3. Hence, the multicast connection can be made.
FIG. 4
is a block diagram of a system using the DTRK. Line interface devices (LINF)
30
1
-
30
7
are connected to the input highways and input terminals of ATM switch
32
of an eight-input, eight-output structure. Line interface devices
34
1
-
34
7
are connected to output terminals of the ATM switch
32
and output highways. The output terminals of the ATM switch
32
are connected to the distribution trunk DTRK
36
, which is also connected to the input terminals of the ATM switch
32
.
The distribution trunk
36
is configured as shown in FIG.
5
. An ATM cell arriving at a terminal
40
is written into a cell buffer
42
and is supplied to a memory controller
44
. The memory controller
44
is connected to a central controller (CC) via a CC interface
46
. A header memory
48
stores tables a and b as shown in
FIGS. 6A and 6B
. The tables a and b are supplied to the header memory
48
from the central controller via the memory controller
44
. In the table a, an address for the table b corresponding to an address (VPI/VCI) in the ATM header is registered. In each address for the table b, the tag and the address (VPI/VCI) of the new ATM cell and the next address for the table b are stored.
The memory controller
44
determines whether the address located in the header of the ATM cell received via the terminal
40
coincides with the addresses for the table a. If the result is affirmative, the memory controller
44
accesses the table b by one of the addresses for the table B registered in the table a. the memory controller
44
reads the tag and address (VPI/VCI) of the ATM cell, which are then output to the terminal
52
via the selector
50
. Subsequently, the memory controller
44
reads the payload of the ATM cell stored in the cell buffer
42
and outputs it to the terminal
52
via the selector
50
. If the next address for the table b is registered in the table a (in other words, if the next address is not the EOC (end of cell)), the memory controller
44
reads the tag and address (VPI/VCI) of the ATM cell of the next address. The tag and address are then output to the output terminal
52
via the selector
50
. Subsequently, the memory controller
44
reads the payload of the ATM cell stored in the cell buffer
42
and outputs it to the terminal
52
via the selector
50
. In the above manner, the ATM cell is copied.
The ATM cell output from the terminal
52
is supplied to the ATM switch
32
shown in FIG.
4
. The tag of the ATM cell indicates to which terminal of the ATM switch
32
should be output. By setting the tag of the ATM cell copied using the distribution trunk
36
to be identical to the tag of the ATM cell switched by the ATM switch
32
, the identical ATM cells can be distributed to a plurality of line interfaces LINF (#1, #4 and #6 in FIG.
4
).
The conventional system using the MSSR switch can copy the ATM cell transferred via an input highway and send copied ATM cells to a plurality of output highways, but cannot send copied ATM cells to a single output highway.
The other conventional system using the DTRK causes a delay due to routing from the ATM switch
32
to the distribution trunk
36
. A further delay is caused when the received ATM cell is copied by the distribution trunk
36
. There is another problem such that the ATM cell is copied by serially reading the tag and the address for the table b, and thus a connection listed in a last part of the table b (indicated by the tag and address) has a delay larger than that of a connection listed in a beginning part thereof (indicated by the address in the table a). The total delay caused by the above factors may extend a tolerable delay defined by the services. There is yet another problem in that the ATM cell
32
has an increased amount of traffic because the ATM cells output by the distribution trunk
36
pass through the ATM switch
32
and are then sent to the output highways via the line interfaces
34
1
-
34
7
. In this case, the traffic of incoming ATM cells via the line interfaces
30
1
-
30
7
from the input highways may be restricted.
It may be considerable to provide distribution trunks to the output highways of the system using the MSSR switch so that the ATM cells are copied at the respective output highways. However, the distribution trunks respectively have header memories, and the whole switch may have an increased circuit scale.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide an ATM switch in which the above disadvantages are eliminated.
A more specific object of the present inventio

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