ATM signal processors

Multiplex communications – Wide area network – Packet switching

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370 942, H04J 324

Patent

active

054043549

ABSTRACT:
An ATM signal processor system for processing ATM data cells which in combination define a data package wherein the last cell of a package is characterized by an identifying code. The cells of different data packages are multiplexed to provide a serial data stream. A server and a buffer store via which the server is fed with the serial data stream are provided. The buffer store has a threshold capacity beyond which cells are discarded. A discarded cell identifier/rejecter serves to identify and store the identity of a data package with which a discarded cell is associated so as to be set thereafter to reject subsequently received cells with the same data package identity until being reset upon receipt of the last cell of the package as indicated by its characteristic identifying code.

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IEEE 1991 Custom Integrated Circuits Conference-"A 0.8-m BiCMOS Sea-Of-Gates Implementation of the Tandem Banyan Fast Packet Switch", Fabio M. Chiussi et al, pp. 3.3.1-3.3.6.
IEEE Global Telecommunications Conference-Dec. 6-9, 1992; "A High-Performance Prototype 2.5 Gb/s ATM Switch for Broadcast Applications", K. Y. Eng et al-pp. 111-115.
IEEE Global Telecommunications Conference; Dec. 6-9, 1992 "Datagram Switching Networks for Broadband Data Communications", M. Decina et al-pp. 104-110.

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