Multiplex communications – Pathfinding or routing
Reexamination Certificate
1999-05-14
2003-06-17
Le, Thanh Cong (Department: 2684)
Multiplex communications
Pathfinding or routing
C370S389000
Reexamination Certificate
active
06580707
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a repeater provided to execute packet routing process in, for example, a computer network or LAN, and more particularly to an ATM repeater using particularly an ATM switch.
BACKGROUND ART
A repeater generally called a router has the hop-by-hop transfer mode as one of packet routing modes. The hop-by-hop transfer mode is a mode of extracting a destination IP address and control information from the input IP packet data, determining the transfer destination in accordance with the extracted destination IP address and control information, and transmitting the IP packet data in a line corresponding to the transfer destination, in a network layer. This process is conventionally implemented by the software process with a processor.
In an ATM repeater, for example, a processor which is a microcomputer is provided to execute the address searching process for the hop-by-hop transfer.
FIG. 1
is a circuit block diagram showing a schematic configuration of a conventional ATM repeater.
In
FIG. 1
, when a plurality of ATM cells arrive via the lines of the upstream side, these cells are transmitted to a cell disassembly/assembly unit (SAR: Segmentation and Reassembly Sublayer)
2
via an ATM switch
3
and reconstructed as the packet.
A processor
1
inputs the reconstructed packet, extracts the IP header information and analyzes the destination IP address. Then, the processor
1
accesses a forwarding table by using the analyzed destination IP address as the key information.
Output line information (Next hop) corresponding to the destination IP address is stored in advance on this forwarding table, the IP sub-network or host to which the destination IP address belongs is searched by the processor
1
, and an output line connected to the IP sub-network or host is determined as the transfer destination. The ATM switch
3
is controlled by the processor
1
so that the packet can be transferred via the output line, and the received packet is disassembled in the SAR
2
into ATM cells, that are transmitted from the ATM switch
3
to the output line.
However, in this conventional ATM repeater, extraction of the destination IP address relating to the hop-by-hop transfer and search of the output line information are entirely executed with the software process using the processor
1
. For this reason, there is a problem that load is applied to the processor
1
and the transfer speed of the hop-by-hop transfer is thereby limited by performance of the processor
1
. A higher-speed processor
1
needs to be used in order to improve the performance of the repeater. If this is used, the cost of the repeater is increased since the processor
1
is expensive, which is very undesirable.
The present invention is accomplished in consideration of this circumstance, and its objet is to provide an ATM repeater which implements acceleration of the hop-by-hop transfer without employing a highspeed processor and which is thereby cheap with high performance.
DISCLOSURE OF INVENTION
In order to achieve the above object, the present invention provides an ATM repeater having the hop-by-hop transfer mode to execute the packet routing process in the network layer, in which a transfer destination searching circuit constituted by a hardware circuit is provided by using at least a content addressable memory, and in which the transfer destination searching circuit extracts the header information from the packet transferred through a line of the upstream side, thereby executing a process of searching for the transfer destination in accordance with the header information.
According to the present invention, the processes of extracting the header information concerning the hop-by-hop transfer and searching for the transfer destination are executed by the hardware processing. For this reason, acceleration of the hop-by-hop transfer can be implemented as compared with a conventional repeater which allows the processes to be executed by the software processing, and the price of the repeater can be lowered since a high-speed processor does not need to be prepared.
The present invention further comprises a processor for executing a transfer destination searching operation for the hop-by-hop transfer, with software, and is characterized in that when the transfer destination information corresponding to the header information extracted from the packet cannot be obtained by the transfer destination searching circuit, the header information is supplied to the processor to execute the transfer destination searching process with the software.
With this constitution, when the transfer destination concerning the hop-by-hop transfer is not searched by the hardware processing employing the transfer destination searching circuit, searching the transfer destination is executed with the software processing of the processor. That is, processes of extracting the header information concerning the hop-by-hop transfer and searching for the transfer destination are executed by cooperation of the hardware processing of the transfer destination searching circuit and the software processing of the processor. For this reason, for example, if the transfer destination information concerning the communications of a comparatively higher frequency is registered in advance in the transfer destination searching circuit and the transfer destination information concerning the communications of a comparatively lower frequency is registered in advance in the processor, the packet concerning the communications of a comparatively higher frequency at a general time can be transferred at a high speed by the hardware processing of the transfer destination searching circuit, and the packet which rarely arrives, i.e. which concerns the communications of a comparatively lower frequency can be transferred by the software processing of the processor. As a result, the transfer destination information corresponding to all the header information items do not need to be registered in advance in the transfer destination searching circuit and thereby the capacity of the content addressable memory in the transfer destination searching circuit can be reduced.
Further, in the present invention, the content addressable memory for reading pointer information corresponding to the header information extracted from the packet, and a compression searching memory for compressing the header information on the basis of a predetermined compression algorithm such as an HASH function and reading pointer information corresponding to the compressed information, are provided in the transfer destination searching circuit. First, the content addressable memory is accessed to search for the pointer information corresponding to the header information. If the pointer information corresponding to the header information cannot be searched by the access to the content addressable memory, the compressed searching memory is also accessed to search for the corresponding pointer information.
With this operation, the following advantages can be achieved. That is, generally, the content addressable memory has small memory capacity and expensive though its operating speed is high. On the other hand, an SRAM or DRAM, which is comparatively cheap and has a large capacity, is used as the compression searching memory. Therefore, by allowing the content addressable memory to store not the transfer destination information of all the communications that are to be processed by the hop-by-hop transfer, but the only transfer destination information concerning some communications of a particularly higher communication frequency, and by allowing the compression searching memory to store the other information items, the memory capacity of the content addressable memory can be reduced and thereby the price of the repeater can be set to be cheap.
Moreover, in the present invention, when the transfer destination searching circuit reads the pointer information from the content addressable memory, the transfer destination searching circuit first accesses the content addressable
Ikeda Katsuhiko
Nogami Kazuo
Cong Le Thanh
Corsaro Nick
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
LandOfFree
ATM repeater using hardware implemented transfer destination... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with ATM repeater using hardware implemented transfer destination..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and ATM repeater using hardware implemented transfer destination... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3107255