ATM reassembly controller and method

Details ATM reassembly controller and method ATM reassembly controller and method

1997-01-03

1999-06-29

Hofsass, Jeffery A.

Multiplex communications

Communication techniques for information carried in plural...

Assembly or disassembly of messages having address headers

370395, 370392, 370397, H04L 1256

Patent

active

059178280

ABSTRACT:
An ATM reassembly controller is disclosed that optimizes the utilization of host memory space and hardware resources such as I/O bus bandwidth, host memory bandwidth, memory system bandwidth and CPU resources. The system combines, whenever possible, the PDU status, PDU data and pointers to the host memory data buffers into a large burst write to the status queue. In addition, multiple status bundles are packed into a host memory buffer for efficient use of memory. An additional benefit of combining and packing information is that CPU resources are conserved by having combined the information the CPU must access into to a contiguous memory area.

REFERENCES:
patent: 5604743 (1997-02-01), Le Guigner et al.
patent: 5633867 (1997-05-01), Ben-Nun et al.
patent: 5751698 (1998-05-01), Cushman et al.

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