ATM node having local error correcting procedures

Details ATM node having local error correcting procedures ATM node having local error correcting procedures

2006-02-07

2006-02-07

Ngo, Ricky (Department: 2663)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S474000

Reexamination Certificate

active

06996111

ABSTRACT:
A node for a telecommunications network has a segmentation and reassembly module (SAR module) to perform segmentation and reassembly (SAR) on cells received by the node, the SAR module particularly providing Virtual Channel Identifier (VCI) and Virtual Path Identifier (VPI) translation (referred to as VCI/VPI translation), and has a direct memory access (DMA) mechanism for a storage external to the SAR module, the SAR module performing a first DMA access when the VCI/VPI translation are representative of an error code correcting (ECC) procedure to be carried out in the node, and the SAR module performing a second DMA access when the VCI/VPI translation corresponds to a message that does not require a local ECC procedure. A coder/decoder module performs an ECC procedure on the cells. A controller controls the coder/decoder module to perform an error correcting procedure in response to the detection of the first DMA access. The first DMA access uses a first address and the second DMA uses a second address. A Reed-Solomon coder-decoder or a Hamming coder-decoder may be used to perform the ECC procedure. An address decoder interprets the VCI/VPI identifiers to control whether or not an ECC procedure is done.

REFERENCES:
patent: 5161156 (1992-11-01), Baum et al.
patent: 5166674 (1992-11-01), Baum et al.
patent: 5539756 (1996-07-01), Glaise et al.
patent: 5754754 (1998-05-01), Dudley et al.
patent: 6157641 (2000-12-01), Wilford et al.

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