ATM node having local error correcting procedures

Details ATM node having local error correcting procedures ATM node having local error correcting procedures

1998-02-04

2002-01-22

Nguyen, Chau (Department: 2663)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S474000

Reexamination Certificate

active

06341132

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The invention relates to telecommunications and more particularly to an ATM node, such as a hub, that includes local error correcting procedures.
BACKGROUND ART
The need for improving the integrity of the data being transmitted through large networks has continuously increased, particularly with the development of international business and other activities dealing with sensitive information.
Such concerns obviously applies to the Asynchronous Transfer Mode (A.T.M.) networks which allow transmission of data of different nature via high speed networks.
FIG. 1
illustrates an Asynchronous Transfer Mode (A.T.M.) backbone
1
which topology is comprised, for clarity sake, of hubs
10
-
50
which are interconnected by means of a set of full duplex opticals links
15
,
16
,
25
,
35
and
45
. The ATM networks provides with the possibility to transfer data through the format of cells based on 53 bytes, the cells being concatenated in messages as represented in FIG.
1
. Assuming for instance that such a message is received by hub
10
and that this message is transferred through the network via hubs
20
,
40
and
50
.
Considering now that an error might occur in the transmission path. In this case, the Data Terminating Equipment (DTE) (not represented) which receives the message from the backbone via hub
50
(for instance) detects the occurrence of the error via its own Error Correcting Code (E.C.C.) mechanisms. This detection normally results in the latter discarding the full message being received, what compels the emitting DTE to send back the whole message, that is to say the full number of cells composing the message being lost in the network. It should be noticed that, should the error only affect a single cell, the full message that includes that cell is being lost, what inevitably affects the overall performance and efficiency of the system.
SUMMARY OF THE INVENTION
Therefore a need appears in the ATM technique for a solution which avoid the lost of the full message when one error occurs anywhere in the transmission path.
Additionally, since the ATM networks that exist in the world are composed of a wide variety of different elements, nodes or hubs, it is also required that newly designed hubs still present the compatibility with the already existing equipments (corresponding to huge investments which the customers wish to keep in operation as long as possible).
This problem is solved by the present invention which uses a particular ECC mechanism that is locally distributed at each level of the hubs that compose the ATM network. Therefore, each hub composing the backbone has the possibility of detecting the occurrence of an error, and to correct it. Additionally, the ECC mechanism of the present invention presents the capability of being disconnected, which allows the possibility of handling two different types of messages, comprising or not the internal ECC codes, thus allowing the use of the hub with other existing hubs which do not incorporate the ECC mechanism of the invention.
Basically, the invention takes advantage of the use of the Virtual Channel Identifier (V.C.I.) and Virtual Path Identifier (V.P.I.) for controlling an error correcting mechanism that is provided in the ATM network node.
This is performed by using a Segmentation and Reassembly (S.A.R.) circuit that contains a Direct Memory Access (D.M.A.) circuit for accessing an external storage. The SAR circuit is programmed so that when the VCI/VPI identifiers are representative of an Error Code Correcting procedure to be locally carried out in node, the SAR circuit performs a first DMA access which is decoded by an address decoder and used for controlling a Reed-Solomon coder and decoder. Conversely, when no ECC procedure is required in the node, the SAR decodes the corresponding VCI/VPI and performs a second DMA access which disables the Reed Solomon decoder.
Therefore, according to the requirements of the particular ATM session being established, there appears the capability to perform local ECC correcting procedures. Additionally, since the traditional SAR circuits—ie components off the shelves—may be used for embodying the invention, a simple and low cost hub having ECC capabilities can be designed. At last, the new hub remains fully compatible with the traditional hubs that form part of the ATM backbone network and which do not incorporate the ECC mechanism of the invention.


REFERENCES:
patent: 5161156 (1992-11-01), Baum et al.
patent: 5166674 (1992-11-01), Baum et al.
patent: 5539756 (1996-07-01), Glaise et al.
patent: 5563887 (1996-10-01), Harasaki
patent: 5699369 (1997-12-01), Guha
patent: 5754754 (1998-05-01), Dudley et al.
patent: 5844897 (1998-12-01), Asamizuya
patent: 6151312 (2000-11-01), Evans et al.
patent: 6157641 (2000-12-01), Wilford et al.
patent: 6230297 (2001-05-01), Bentall et al.
patent: 2703544 (1994-10-01), None

Affiliated with

Also associated with

Rating

ATM node having local error correcting procedures does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with ATM node having local error correcting procedures, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and ATM node having local error correcting procedures will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2856660