ATM node and routing data registering apparatus

Multiplex communications – Pathfinding or routing – Switching a message which includes an address header

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370409, H04L 1256

Patent

active

058055924

ABSTRACT:
A CPU sets one of first and second memories as an "active system memory" and the other as a "standby system memory". Data about a combination of the VPI/VCI and TAG data is registered in and deleted from only the memory set as the "active system memory". The CPU, only when a null entry exists in a position satisfying a VPI/VCI increasing sequence with an increased address value, registers this null entry in the active system memory with data about new combination of the VPI/VCI and the TAG data. Whereas if there is no such null entry, the CPU reads the data about all the combinations of the VPI/VCI and the TAG data which are registered in the active system memory, re-sorts the read data and the data about the new combinations in the VPI/VCI increasing sequence and write the data from the head address in the standby system memory in a sorting sequence. The CPU, when finishing this writing process, resets the memory so far working as the standby system to an active system memory and the memory so far working as the active system to a standby system memory.

REFERENCES:
patent: 5515370 (1996-05-01), Rau
patent: 5541915 (1996-07-01), Storm
patent: 5550821 (1996-08-01), Akiyoshi

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