ATM network system

Details ATM network system ATM network system

1998-09-11

2002-07-02

Cangialosi, Salvatore (Department: 2661)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S397000

Reexamination Certificate

active

06414959

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an ATM (Asynchronous Transfer Mode) network system capable of determining a clock synchronization topology (clock supply route) required to transfer audio data and video data through an ATM network.
2. Description of the Related Art
Currently, ATM networks have been developed and are available in the market as transfer media of multimedia applications. The various utilization needs are made of ATM networks. For example, not only LAN data are transferred via ATM networks, typically known as the Internet, but also the ATM network are used in application software of synchronization systems for audio data and video (picture) data. In this case, in order that application software of synchronization systems are transmitted/received in proper manner between these terminals, clock synchronization must be established between terminals so as to transmit/receive data. As a result, in the case that an ATM network is employed in order to repeat data in a synchronization system, this ATM network is required to establish a clock synchronization. As a consequence, clock synchronization topology within the ATM network should be established, which can be hardly influenced by external factors such as a failure, or a defect.
Conventionally, when an ATM network designer tries to design an ATM network, this designer sets a clock synchronization network of ATM switching units (i.e., nodes, will be referred to as “switching units” hereinafter) within this ATM network, and switching units clock synchronization sources every switching unit. Concretely speaking, the ATM network designer presets such a switching unit that constitutes the clock synchronization source, and also determines a clock extracting port (namely, port used to receive clocks from other switching units) of the other respective switching units in such a manner that the clock synchronization topology may own exclusive intention. At this time, the ATM network designer also presets clock extracting ports subsequent to a second priority order, assuming that a failure may occur in the clock supply routes of the respective switching units. In the case that the clock cannot be extracted from the presently used clock extracting port, the clock may be extracted from another clock extracting port having a priority order subsequent to that of this clock extracting port under use.
However, the conventional ATM networks own the following problems. That is, as previously explained, the switching process operations of the clock extracting ports are carried out in the respective switching units. At this time, in such a case that a switching unit for executing the switching process operation is located in an upper stream of other switching units, the adverse influence is given to other switching units existing in a down stream.
FIG. 13
is an explanatory diagram for indicating the problem as to the clock synchronization network in the conventional ATM network. In
FIG. 13
, this ATM network has the switching units (nodes)
1
to
6
. In this ATM network, the clock supply route (clock synchronization topology) having the first priority order, which is directed from the switching unit
1
to the switching unit
4
, is set, whereas the clock supply route having the first priority order, which is directed from the switching unit
1
to the switching unit
5
, is set. Also, the clock supply route having the second priority order, which is directed from the switching unit
4
to the switching unit
6
, is set; whereas the clock supply route having the second priority order, which is directed from the switching unit
5
to the switching unit
2
, is set.
While the clock supply route having the first priority order is used in this ATM network, when a failure happens to occur in the clock supply path connected between the switching unit
2
and the switching unit
3
, the switching unit
3
cannot receive the clock supplied from the switching unit
2
. As a result, the switching unit
3
switches the clock extracting port in accordance with the conditions set to the own switching unit
3
, so that the clock supply route is switched to the clock supply route having the second priority order, through which the clock is received from the switching unit
4
.
However, the switching unit
3
has no structure capable of transferring to the switching unit
4
and the switching unit
5
such a fact that the failure occurs in the clock supply path. As a consequence, even after the switching unit
3
is brought into such a condition that the clock is received from the switching unit
4
, this switching unit
4
maintains such a condition for receiving the clock from the switching unit
3
. On the other hand, since the switching unit
5
maintains the setting conditions before the failure happens to occur, the clock received from the switching unit
6
is not supplied to the switching unit
4
. As a result, the clock loop is produced between the switching unit
3
and the switching unit
4
, and thus both the switching units
3
and
4
are disconnected from the clock synchronization network, so that these switching units
3
and
4
cannot be synchronized with other switching units
1
,
2
,
5
, and
6
.
In the ATM network shown in
FIG. 13
, when a failure happens to occur in the switching unit
1
, there are certain possibilities that the clocks are not supplied to other switching units
2
to
6
.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an ATM network system capable of avoiding such a problem that when a failure happens to occur in a clock supply route, a switching unit disconnected from a clock synchronization network will occur.
A first aspect of the present invention is featured by such an ATM network system having a clock synchronization source and a plurality of nodes synchronized with the clock synchronization source, and set a plurality of routes for supplying a clock from said synchronization source to each of said nodes. In this ATM network system, each of the nodes, when detecting a failure occurred in a presently used route, gives a failure signal to an other node to be supplied a clock from the node through a failure-detected route, and changes the failure-detected route into an other route. Each of said nodes, when received a failure signal from an other node, changes the failure-detected route into an other route in accordance with the failure signal.
In accordance with the first aspect, when the node which has detected the failure of the clock supply route changes the route used by the node, this node supplies the failure signal to another node located in the down stream of the node in such a node where the failure occurs. Then, another node changes the route used by the node based upon the failure signal. As a result, even when the node which has detected the failure is brought into such a condition that since the route is changed by this node and no clock is supplied to another node, another node can receive the clock by changing the node. As a consequence, it can be prevent another node from being deviated from the clock synchronization network.
In this case, as the node, for instance, ATM transfer units such as an ATM switching unit, ATM-HUB, and an ATM router may be employed, which constitute an ATM network. Also, as the clock synchronization source, a node having a clock generating source, or a node for receiving a clock from a user terminal unit may be employed.
A second aspect of the present invention is featured by such a clock supply route determining method in an ATM network system in which said ATM network is constructed based on the private network-to-network interface specification (PNNI). In the ATM network system, a plurality of nodes for constituting the ATM network forms a pier group. Each of nodes within the pier group owns data of shortest routes defined from the own node to each of other nodes. Any of the nodes within the pier group is set as a pier group leader, and this pier group leader is set as a clock sync

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