ATM network interface

Details ATM network interface ATM network interface

1994-09-01

1997-04-08

Olms, Douglas W.

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

370396, 370401, 370419, H04L 1256

Patent

active

056195001

ABSTRACT:
A novel ATM network provided which includes one or more ATM gateways for interfacing a plurality of T1 or fractional T1 signals with a higher bandwidth ATM network switch. In order to provide high speed and bandwidth utilizing relatively inexpensive and standard components, the data is stored in a memory, such as a video RAM, and pointers are utilized to indicate the type of each piece of data stored in the memory, including its priority for transmission to an ATM switch. In one embodiment of this invention, a plurality of pointer pools are used, each corresponding to a data type having a given priority. Pointers are placed into an appropriate one of the pools to define the order in which data will be transferred to the ATM switch in accordance with the priority of the data type and the receiving bandwidth of its destination in the ATM network. In one embodiment an HDLC controller is used which is suitable for framing a plurality of channels of data received on an incoming data path, such as a T1 channel. In order to minimize processing hardware requirements, a single HDLC controller is used to provide appropriate framing of each channel in a multiplexed fashion, with intermediate HDLC states being stored in a temporary state memory for retrieval when the next set of bits for a given channel is received for processing by the HDLC controller. A plurality of buffer memories are used for storing intermediate data corresponding to each of the incoming channels.

REFERENCES:
patent: 5083269 (1992-01-01), Syobatake et al.
patent: 5126999 (1992-06-01), Munter et al.
patent: 5233606 (1993-08-01), Pashan et al.
patent: 5278828 (1994-01-01), Chao
patent: 5327421 (1994-07-01), Hiller et al.
patent: 5357506 (1994-10-01), Sugawara

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