ATM linked list buffer system

Details ATM linked list buffer system ATM linked list buffer system

2007-05-08

2007-05-08

Ho, Duc (Department: 2616)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S395640, C370S412000

Reexamination Certificate

active

09804929

ABSTRACT:
A linked list buffer circuit can be configured to store different linked lists. The buffer includes insert logic and an insert state machine to add ATM cells to the linked lists in the buffer. Extract logic and an extract state machine allow for the removal of ATM cells from the linked lists in the buffer. Because, ATM cells can have different levels of priority, programmable monitor circuitry is provided to monitor the linked lists in the buffer. The monitor circuitry keeps track of buffer and list capacity, and also keeps track of cell loss priority and delay priority cells of the buffer and the linked lists. This information is used to drop received cells if necessary. The linked list monitor circuitry can be configured based upon the linked list configuration of the buffer. The linked list monitor can be configured by changing threshold levels provided to counter/comparator circuitry. Assignments of internal counter circuitry are also programmable based upon the buffer configuration.

REFERENCES:
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patent: 5893162 (1999-04-01), Lau et al.
patent: 6021115 (2000-02-01), Simpson et al.
patent: 6151301 (2000-11-01), Holden
patent: 2002/0031132 (2002-03-01), McWilliams
patent: 0 472 408 (1992-02-01), None
patent: 0 472 408 (1992-02-01), None

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