ATM direct access line system

Details ATM direct access line system ATM direct access line system

2000-06-05

2002-07-16

Olms, Douglas (Department: 2661)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S397000, C370S523000

Reexamination Certificate

active

06421344

ABSTRACT:

BACKGROUND
At present there are telecommunications services available from telecommunications networks that require direct connection to the customer equipment. In some cases, a specific trunk or group of trunks connect a network switch to a customer switch and have attributes that are unique to that customer. These attributes include, but are not limited to, customized dialing plans, billing arrangements, virtual private networks, and specialized routing functions. These trunks and trunk groups are known as Dedicated Access Lines (DALs).
A single network switch may serve many DAL customers over a large geographical area. Typically, a switch located in one city may serve many DAL customers in another city. The customers in the other city may each share a common transmission facility in order to be connected to the network switch. The cost of the transmission facility is based on the quantity of circuits and the distance they are carried. Economic benefit is derived from minimizing the number of these circuits. In current systems, the DAL circuits are provided using the well known T1 Super Frame (SF) or T1 Extended Super Frame (ESF) format. Both SF and ESF transport customer traffic in the DS
0
circuit.
At present, Asynchronous Transfer Mode (ATM) technology is being used to provide high speed transport for traffic carried by T1 ESF or SF. This ATM transport technique uses an ATM interworking multiplexer (ATM mux) to convert the DS
0
traffic into ATM cells that can be transported over a broadband connection. At the terminating end of the broadband system, the ATM cells are re-converted back into DS
0
format by another ATM mux for delivery to the destination system. Thus, DALs using SF or ESF may be transported over an ATM broadband connection by passing through ATM muxes.
Many of these DAL transport formats require the transmission of a continuous signal even when no user traffic is being transported. For example, a voice DS
0
connection continuously transmits a 64,000 bit/second signal whether or not the DS
0
connection is transporting any user traffic. This causes a problem in the above-described transport scenario. The ATM mux will convert the voice DS
0
signal into ATM cells for transport, and since the DS
0
signal is continuous, a continuous stream of ATM cells must be transported by the ATM network. This occurs even when no user traffic is being transported. The idle DS
0
signal is still transported in ATM cells. When the voice DS
0
is transported using SF or ESF format using robbed bit signaling, the idle state can be detected by monitoring the DS
0
's A and B signaling bits in the 6th and 12th frames of an SF or ESF. The state of the A and B bits indicates when the DS
0
is active or off-hook and when the DS
0
is idle or on-hook.
Currently, when a voice DS
0
from an SF or ESF T1 using robbed bit signaling is converted to ATM cells, a continuous stream of ATM cells must be transported by the ATM broadband connection. This situation represents a waste of resources. At present, there is a need for an ATM system that can transport continuous signal voice robbed bit signaling formats when they carry user traffic, but not when they do not carry user traffic. Current solutions to this problem include the use of an ATM interworking multiplexer that detects robbed bit signaling and enables and disables associated VPI/VCI virtual connections. This solution is lacking because it is a point-to-point system, and there is no opportunity to exert control over the mux for the purpose of routing.
Currently, ATM Circuit Emulation Service and Virtual Trunking Service have been defined to transport a DS
0
circuit within a T1 on ATM. These methods assume that the DS
0
circuit is managed by out-of-band signaling (SS7 or PRI, etc.) and do not address the requirements of DS
0
circuits that are managed by in-band robbed bit signaling. This requires T1 frame alignment to maintain the A, B, C & D signaling bits in the signaling frames. DS
0
frame data entering the ATM system must remain frame aligned with the corresponding DS
0
frame data that exits the ATM system.
F
5
OA&M system management ATM cells are well known in the art. The OA&M cell header contains:
VPI=VPI of the DS
0
's ATM path
VCI=VCI of the DS
0
's ATM path
PTI=
101
F
5
end to end OA&M flow
Cell OA&M field: OAM type=System Management 1111
Cell OA&M field: Function type=0001 frame sync
User Data sent in the OA&M cell contains:
Octet 1
AAL1 SAR PDU =
Sequence number and Sequence number
protection
Octet 2-5
DS0 =
Far end DS0 identifier
[Mux id & DS0 id]
Octet 6
Status =
Status of this DS0 circuit
[on-hook, off-hook, maint OOS,
T1 Frame slip, T1 Frame Resync,
Initial Frame Sync, etc]
Octet 7
Frame # =
Number of the T1 frame that first octet in the
next user cell came from
[1-12 SF or 1-24 ESF]
Octet 8
Frame Type =
This ends framing SF or ESF
Octet 9
Signaling Type =
This ends signaling type
[Loop start, Ground start, Wink start, etc]
Octets 10-48 have been reserved for future use.
SUMMARY
The invention includes a telecommunications system for routing information in an asynchronous transfer mode (ATM) system with ATM cells that contain a virtual path identification/virtual channel identification (VPI/VCI), wherein the information is from a first DS
0
in a first T1 Superframe/Extended Superframe (ESF/SF) system that uses robbed bit signaling and is routed by the ATM system to a second DS
0
in a second T1 Superframe/Extended Superframe (ESF/SF) system that uses robbed bit signaling. The system comprises a first ATM interworking multiplexer that is operational to monitor the robbed bit signaling from the first ESF/SF system, to generate and transmit a message indicating an off-hook state, to receive a message identifying the first DS
0
and the VPI/VCI, to convert the information from the first DS
0
into ATM cells with the VPI/VCI, to generate an F
5
OA&M cell containing the VPI/VCI and frame alignment information, and to transmit the ATM cells. The system comprises a second ATM interworking multiplexer that is operational to receive a message identifying the VPI/VCI and the second DS
0
, to receive the ATM cells with the VPI/VCI , to convert the ATM cells to information for the second DS
0
using the frame alignment information, and to transmit the second DS
0
to the second ESF/SF system. The system comprises a signaling processor that is operational to receive the message from the first ATM multiplexer, to select the VPI/VCI and the second DS
0
in response to the off-hook state, to generate and transmit the message to the first ATM multiplexer identifying the first DS
0
and the VPI/VCI, and to generate and transmit the message to the second ATM multiplexer identifying the second DS
0
and the VPI/VCI. The system comprises a first link from the first ATM multiplexer to the signaling processor operational to transfer the messages, and a second link from the second ATM multiplexer to the signaling processor operational to transfer the message, and an ATM routing system that is operational to route the ATM cells between the first ATM multiplexer and the second ATM multiplexer based on the VPI/VCI.
In some embodiments the first ATM multiplexer and the second ATM multiplexer are operational to correct T1 slips, synchronization in frame alignment, and handle ATM cell loss. In some embodiments, the first ESF/SF system includes a first switch that sends a route request message to the telecommunications system, and the signaling processor that is operational to receive the route request message from the first switch and to select the first DS
0
, the VPI/VCI, and the second DS
0
in response to the route request message


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patent: 4720850 (1988-01-01), Oberlander et al.
patent: 4730312 (1988-03-01), Johnson
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patent: 4926416 (1990-05-01), Weik
patent: 5051983 (1991-09-01), Kammerl
patent: 5115431 (1992-05-01), Williams et al.
patent: 5

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