Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1999-02-09
2004-03-23
Kizou, Hassan (Department: 2662)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S397000, C370S399000, C370S395500, C370S395520, C370S395600
Reexamination Certificate
active
06711167
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an ATM (asynchronous transfer mode) communication apparatus realizing the function of converting ATM cells into an IP (internet protocol) packet adapted to a communication protocol of a computer network such as LAN (local area network), and the function of converting the IP packet into the ATM cells.
2. Description of Related Art
In an ATM communication network, a communication protocol for transmitting data is constituted of a plurality of layers, each of which has an inherent function. One layer is realized by utilizing the function of a layer inferior to the first named layer by one layer.
Of the plurality of layers, a low level layer which is the most remote layer from a user's side, includes a physical layer, an ATM layer and ATM adaptation layer.
The physical layer is a layer for providing a resource for transferring an ATM cell which is a unit of information transmission, and specifically, executes generation of a signal format suitable to a transmission medium, receiving of a signal, an encoding, or generation and elimination of a transmission frame. Furthermore, the physical layer checks whether or not the information included in the cell is effective, and transfers the cell carrying the effective information (effective cell) to the ATM layer.
The ATM layer is a layer superior to the physical layer by one layer, and executes a multiplexing and a separation of cells and generation and extraction of an ATM header indicating the destination of the ATM cell.
The ATM adaptation layer is positioned between the ATM layer and a layer superior to the ATM layer, and has the function of segmentation and reassembly of the ATM cell and of verifying the correctness of the ATM cell to inform the result of the verification to the superior layer.
The ATM cell includes in an ATM header a label for identifying a virtual channel (VC) or a virtual path (VP) to which the ATM cell itself belongs. This label is constituted of a virtual channel identifier (VCI) or a virtual path identifier (VPI), and an individual VC is unambiguously identified by a combination of VPI and VCI. In the following, the number given to a respective VC is called a VC number (VC No.)
On the other hand, it has been known to use a router as a technology for connecting an internet to a small scaled computer network such as SOHO (small office home office). Here, if the internet is the ATM communication network and the computer network is an ethernet, the router includes, in addition to the above mentioned functions of the physical layer, the ATM layer and the ATM adaptation layer, the function of converting ATM cells sent from the ATM communication network, into an IP (internet protocol) packet adapted to a communication protocol of the computer network, and the function of converting the IP packet sent from the computer network, into the ATM cells.
In the following, the ATM communication apparatus realizing the function of converting the ATM cells into the IP packet and the IP packet into the ATM cells, will be described with reference to the router as one example.
FIG. 5
is a block diagram showing the construction of the router which is one example of the prior art ATM communication apparatus.
FIG. 6
is a table illustrating one example of the construction of the lookup table provided in a sending/receiving controller shown in FIG.
5
.
FIG. 7
is a diagram illustrating the relation between the IP packet and the ATM cells.
Referring to
FIG. 5
, the prior art router includes a SAR (segmentation and reassembly) module
11
for executing the processing of a low level layer, a CPU
12
for executing segmentation and reassembly of the IP packet and the processing of a high level layer, a memory
13
for temporarily storing data used in the processing of the CPU
12
, a first ethernet interface
14
1
and a second ethernet interface
14
2
which are an interface circuit for sending data to a network (ethernet) and receiving data from the network (ethernet), an ATM
25
interface
14
3
which is an interface circuit for sending data to a network of the ATM
25
specification and receiving data from the network of the ATM
25
specification, and a recording medium
15
storing a processing program executed in the CPU
12
.
Here, the SAR module
11
, the CPU
12
, the memory
13
, the first ethernet interface
14
1
, the second ethernet interface
14
2
, the ATM
25
interface
14
3
, the recording medium
15
are connected to an I/O bus
16
which is a data transfer medium. Incidentally, the first ethernet interface
14
1
, the second ethernet interface
14
2
, the ATM
25
interface
14
3
are provided dependently upon the network to which the router is connected, and therefore, it is not limited to this construction.
The SAR module
11
includes a physical interface
17
which is an interface circuit for sending data to the ATM communication network and receiving data from the ATM communication network, a sending/receiving controller
18
for executing the proceedings of the ATM layer and the ATM adaptation layer, and a bridge
19
which is an interface circuit for sending data to the CPU and receiving data from the CPU.
The sending/receiving controller
18
includes a lookup table for recording the relation between VCI/VPI and the VC number used in the router (see
FIG. 6
) and a VC table recording the VC number, the address of a memory region for storing the data of the received ATM cell and IP packet, and VC associated data, such as the number of ATM cells and the packet length.
Incidentally, as shown in
FIG. 7
, the ATM cell which becomes a heading cell of the IP packet (simply called a “heading cell” hereinafter), includes an IP header composed of the destination information of the IP packet itself, control information, etc. On the other hand, the ATM cell which becomes a last cell of the IP packet (simply called a “last cell” hereinafter), includes a trailer composed of the packet length information of the IP packet itself, error check information, etc.
Now, an operation of the prior art router mentioned above will be described with reference to FIG.
8
and FIG.
9
.
FIG. 8
is a flow chart illustrating the processing procedures of the router shown in
FIG. 5
for converting the ATM cells to the IP packet, and
FIG. 9
is a flow chart illustrating the processing procedures of the router shown in
FIG. 5
for converting the IP packet to the ATM cells.
In the processing procedures shown in
FIG. 8
for converting the ATM cells to the IP packet, if the sending/receiving controller
18
in the SAR module
11
receives the ATM cell through the physical interface
17
, the sending/receiving controller
18
analyzes the content of the ATM header (step S
21
), and discriminates whether or not the received ATM is the heading cell of the IP packet (step S
22
).
If the received ATM is the heading cell of the IP packet, the sending/receiving controller
18
reserves, in the memory
13
, a predetermined amount of memory region for storing the data of the ATM cell which constitutes the IP packet (step S
23
). If the received ATM is not the heading cell of the IP packet, the processing of the step S
23
is not executed, and the processing goes into a next processing (step S
24
).
In the step S
24
, the sending/receiving controller
18
refers to the lookup table, and obtain the VC number corresponding to VCI/VPI of the received ATM cell, and further, refers to the VC table on the basis of the obtained VC number, and write the data of the received ATM into the memory region reserved in the step S
23
. When the received ATM is the heading cell of the IP packet, the data is written from the heading address of the reserved memory region. The address of the memory region is recorded in the VC table as the data corresponding to the VC number. After the data of the ATM cell has been written, the address of this memory region is updated to a succeeding address. On the other hand, when the received ATM is not the heading cell of the IP packet, the
Ikeda Chinatsu
Tomimitsu Yasuharu
Kizou Hassan
Logsdon Joe
McGinn & Gibb PLLC
NEC Electronics Corporation
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