1995-09-05
1998-06-23
Baker, Stephen M.
Excavating
370509, H03M 1300, H04L 700
Patent
active
057712492
ABSTRACT:
An asynchronous transfer mode (ATM) cell synchronizing method and circuit used in a digital network system in which: an 8 bit ATM cell stream of a received signal is inputted into a five-stage D flip-flop and outputted to a first adder (exclusive OR) circuit through a remainder operation circuit; the adder circuit evaluates exclusive OR of the output of the remainder operation circuit and the inputted 8 bit ATM cell stream, the result of such an evaluation is inputted into a one-stage D flip-flop through a second adder; and the output of this one-stage D flip-flop is inputted into a CRC arithmetic operation circuit having a generating polyominal X.sup.8 +X.sup.2 +) X+1 and also into a decoder. The output of the CRC arithmetic operation circuit is inputted back to the second adder, and a cell synchronizing pulse is outputted from the decoder.
REFERENCES:
patent: 5282215 (1994-01-01), Hyodo et al.
patent: 5345451 (1994-09-01), Uriu et al.
Bahl et al., "Shortened Cyclic Code with Burst Error Detection and Synchronization Recovery Capability", IBM Technical Disclosure Bulletin, vol. 16, No. 6, Nov. 1973, pp. 2026-2027.
Ely et al., "High-Speed Decoding Technique for Slip Detection in Data Transmission Systems Using Modified Cyclic Block Codes", Electronics Letters, vol. 19, No. 3, Feb. 3, 1983, pp. 109-110.
Baker Stephen M.
Toyo Communication Equipment Co., Ltd.
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