Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2001-03-13
2003-04-08
Vanderprye, Ken (Department: 2661)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S398000, C370S535000
Reexamination Certificate
active
06546011
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a switching system′, or more in particular to an ATM (Asynchronous Transfer Mode) switching system used with the speech path equipment of a wide-bandwidth ISDN exchange and, especially, an ATM switching system suitable for accommodating a plurality of types of input-output links having different transmission rates.
A “TDM Switching System” proposed by JP-A-59-135994 is known, for example, as an ATM switching system applied to the wide-bandwidth ISDN exchange.
This switching system comprises a multiplexer for multiplexing a fixed-length packet (hereinafter referred to as “the cell”) inputted from each input line, a buffer memory for inputting a multiplexed cell, a demultiplexer for periodically separating the cells outputted from the buffer memory among output lines, and a buffer memory control circuit for controlling the buffer memory for each output line. The buffer memory control circuit, which includes FIFO (First In First Out) memories corresponding to the output lines, inputs a write address for the buffer memory into a FIFO memory corresponding to the cell output destination judged from the header information of a cell when the cell is written into the buffer memory. Also, the cell output from the buffer memory corresponding to each output line is produced at predetermined time intervals so that a read address is outputted to the buffer memory from the FIFO memory corresponding to each output line in timing with the cell output.
According to the above-mentioned prior art, the reading of a cell from the buffer memory is controlled to a predetermined timing for each output line. When an attempt is made to accommodate a plurality of types of output links (output lines) different in transmission rate in a switching system having the above-mentioned configuration, therefore, the problem is posed of a very complicated hardware configuration of the buffer memory control circuit.
A packet switching system capable of accommodating a plurality of types of input/output links having different transmission rates is proposed in JP-A-63-64439, for example, as a system for controlling the write and read operations of a packet with a buffer memory using a control memory.
In the above-mentioned packet switching system, a plurality of input and output ports of a switch unit are matched one to one with input and output lines respectively, and packets are inputted and outputted to these input/output ports at a rate equal to the data transmission rate of the input/output lines connected thereto.
In order to realize this switching operation, according to the prior art, the number of an input line providing an objective of the packet write process or an output line providing an objective of the packet read process within a predetermined regular time interval and the R/W designated data are stored in the control memory according to the processing sequence in such a manner as to generate the R/W process at a frequency corresponding to the data transmission rate of each line. The contents (the line numbers and the R/W designated data) of the control memory are sequentially read with the counter output value as an address and packets are written into or read from the buffer memory for the input/output lines designated by the line number thus read out.
More specifically, the switching system described above is such that the buffer memory access is sequentially controlled in such a manner that packets are processed at the switching unit input port (or switch unit output port) connected to a high-speed input line (or output line) at a higher frequency than at the switch unit input port (or switch unit output port) connected to a low-speed input line (or output line).
SUMMARY OF THE INVENTION
An object of the present invention is to provide an ATM switching system capable of a cell switching operation in accordance with the cell transmission rate of an output line to be accommodated.
Another object of the present invention is to provide an ATM switching system which can accommodate output lines of a plurality of different transmission rates including, say, 600 Mbps, 150 Mbps and 50 Mbps with a comparative freedom.
In order to achieve the above-mentioned objects, an ATM switching system according to the present invention comprises a switch unit including a plurality of switch unit input ports and switch unit output ports having a first transmission rate respectively, a plurality of input lines (input links), a plurality of output lines (output links), and at least one conversion means inserted between at least one of the output lines and at least one of the switch unit output ports and having a second transmission rate different from the first transmission rate for converting a cell train of the first transmission rate into a cell train of the second transmission rate. The switch unit includes multiplexing means for multiplexing and outputting a plurality of cell trains inputted from the switch unit input ports as a cell train, a shared buffer memory for temporarily storing the cell trains outputted sequentially from the multiplexer means, demultiplexing means for distributing in circulation the cells read from the shared-buffer memory among the switch unit output ports, and a buffer memory control circuit for controlling the write and read operations of cells from the shared buffer memory; and the buffer memory control circuit includes control table means for outputting an identifier of the output line required to output a cell read from the shared buffer memory in accordance with the cell output timing to the switch unit output port, write means the cell train outputted from the multiplexing means into the buffer memory in such a manner as to form a cue chain of cells for each output line required to be outputted thereby, and read means for reading the cells from the cue chain in the shared buffer memory in accordance with the output line identifier read sequentially from the control table means.
According to the switching system described above, at least one conversion means for converting an input cell train into a cell train of the first trans-mission rate may be connected between at least one of the input lines having a transmission rate different 20 from the first transmission rate and at least one of the switch unit input ports.
In an ATM switching system according to the present invention, assuming that the internal links connected to the output ports of the switch unit are set to the same transmission rate and that the output cells from the internal output links are bundled together by a multiplexer (a kind of conversion means), for example, the cell transmission rate at the output lines connected to the multiplexer can be increased. on the other hand, the output cell from an internal output link may be distributed among a plurality of output lines by a demultiplexer (a kind of conversion means) thereby to reduce the cell transmission rate at each output line. Assuming that a quadruple multiplexer is installed for an internal output link having a transmission rate of 150 Mbps, for example, it is possible to realize an output line having a transmission rate of 600 Mbps. Also, an output line having a transmission rate of 50 Mbps is realized by providing a demultiplexer of three divisions.
In this case, the technical task is how to control the buffer by a buffer memory control circuit. According to the present invention, the above-mentioned multiplexer or demultiplexer is installed at the output port side of the ATM switching unit and the cell queue chain access is controlled in accordance with the output line (output link) connected to the multiplexer or demultiplexer respectively. The above-mentioned control table means has stored therein an output line identifier corresponding to the timing of cell output to the switch unit output ports. According to a counter value, for instance, a switch unit output port is selected and a table addressed sequentially in circulation, so that in timing with the cell output to each output port,
Gohara Shinobu
Horiki Akira
Kato Takao
Kuwahara Hiroshi
Mori Makoto
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