ATM cell sending system

Multiplex communications – Data flow congestion prevention or control – Control of data admission to the network

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370392, 370398, 711108, H04L 1256

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active

059533153

ABSTRACT:
An ATM cell sending system includes a first memory, a second memory, a retrieval circuit, and a memory control circuit. The first memory temporarily stores an input cell, outputs a cell storage address, and, in response to input of the cell storage address, outputs the cell stored at the input cell storage address. The second memory stores the cell storage address from the first memory and outputs the readout cell storage address to the first memory. The retrieval circuit uses an address corresponding to a reservation time for cell sending as a start address to retrieve a first free address after the reservation time from the second memory. The memory control circuit writes the cell storage address of the first memory at the free address of the second memory, which is retrieved by the retrieval circuit, and reads out the cell storage address of the first memory from an address of the second memory which corresponds to a current time.

REFERENCES:
patent: 5381407 (1995-01-01), Chao
patent: 5467349 (1995-11-01), Huey et al.
patent: 5513134 (1996-04-01), Cooperman et al.
patent: 5530698 (1996-06-01), Kozaki et al.
patent: 5535197 (1996-07-01), Cotton
patent: 5581550 (1996-12-01), Boyer et al.
H. Jonathan Chao, "Design of Leaky Bucket Access Control Schemes in ATM Networks", IEEE ICCC '91, Mar. 1991, pp. 180-187.

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