ATM cell receiver system with source clock recovery

Details ATM cell receiver system with source clock recovery ATM cell receiver system with source clock recovery

1996-12-03

2000-05-09

Vu, Huy D.

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

370516, H04L 1238, H04J 306

Patent

active

060613521

ABSTRACT:
A cell disassemble circuit in a cell receiver system detects the number of lost cells from information for detecting cell loss included in received cells, and separates a payload from a header in each of the received cells. The number of lost cells indicates the number of cells lost on a transmission path from the transmission side to the cell receiver system. A buffer stores the number of detected lost cells and data inserted in the payloads. A phase locked loop recovers a source clock corresponding to the rate of fixed rate information based on a use level of the buffer. A counter circuit generates a clock for reading data from the first buffer from the recovered source clock. Also, the counter circuit stops outputting the read clock to the buffer for a time period corresponding to the number of lost cells.

REFERENCES:
patent: 5654962 (1997-08-01), Rostoker et al.
patent: 5657316 (1997-08-01), Nakagaki et al.
patent: 5774466 (1998-06-01), Hamamoto et al.
H. Uematsu et al, "CLAD Implementation and Experimental Results in ATM Networks", Institute of Electronics, Information and Communication Engineers Report, B-I, vol. J77-B-I, No. 11. Nov. 1994, pp. 684-694.

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