ATM cell multiplexing device capable of reducing an accessing sp

Details ATM cell multiplexing device capable of reducing an accessing sp ATM cell multiplexing device capable of reducing an accessing sp

1992-03-30

1994-06-21

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 581, H04J 304

Patent

active

053233999

ABSTRACT:
On time division multiplexing first through N-th input signals, each having a bit rate V to represent successive ATM cells, a multiplexing section (12, 13') multiplexes the first through the N-th input signals and a dummy input signal into a time division multiplexed signal having another bit rate V.times.(N+1) and comprising first through N-th multiplexed cells and a dummy multiplexed cell. The first through the N-th and the dummy multiplexed cells are derived from the first through the N-th and the dummy input signals, respectively. A controller (16') successively writes valid cells of the first through the N-th multiplexed cells in an FIFO memory (15) as written cells at a writing rate equal to the bit rate V.times.(N+1) for a writing time interval defined by the first through the N-th multiplexed cells and reads the written cells from the FIFO memory in a first-in first-out order as a read-out signal at a reading rate equal to the bit rate V.times.(N+1) for a reading time interval defined by the dummy multiplexed cell. A converter (17) converts the read-out signal into a multiplexed output signal having the bit rate V.

REFERENCES:
patent: 5067123 (1991-11-01), Hyodo et al.
patent: 5086424 (1992-02-01), Motohashi et al.
patent: 5121385 (1992-06-01), Tominaga et al.
Suzuki et al., "Output-buffer switch architecture for asynchronous transfer mode", IEEE International Conference on Communications, CHZ 655-9 (1989), pp. 0099-0103.

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