ATM cell multiplexer

Details ATM cell multiplexer ATM cell multiplexer

2000-03-28

2004-09-21

Hsu, Alpus H. (Department: 2665)

Multiplex communications

Data flow congestion prevention or control

Control of data admission to the network

C370S394000, C370S395100

Reexamination Certificate

active

06795398

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an ATM cell multiplexer, and in particular to an ATM cell multiplexer operated on ATM-PON (Asynchronous Transfer Mode-Passive Optical Network) layer.
In a construction of an optical access network represented by the FTTH (Fiber to the Home) for realizing a high informative communication service, the ATM-PON technique has been indispensable as a means for realizing a large capacity of data communication.
In this case, a technique is required which multiplexes an ATM cell from a subscriber and performs a mapping on the ATM-PON layer to the ATM cell as a data cell.
2. Description of the Related Art
FIG. 12
shows an optical subscriber interface or an optical network unit ONU which multiplexes an ATM cell and performs a mapping on the ATM-PON layer to the ATM cell as a data cell, as mentioned above.
In order to transfer the ATM cell from a subscriber to a subscriber terminal equipment or an optical line terminal (OLT), the optical subscriber interface ONU is provided with an ATM cell multiplexer
11
, an up data assembly portion
12
, and a down delay take-in portion
14
.
Data taken in at the take-in portion
14
are further outputted to cards {circle around (1)} and {circle around (2)} attached outside, and input data from the cards {circle around (1)} and {circle around (2)} are multiplexed at the ATM cell multiplexer
11
.
The data cell multiplexed at the ATM cell multiplexer
11
are outputted to the subscriber terminal equipment as up data at a timing adjusted at a delay adjuster
13
in the up data assembly portion
12
, subject to a delay adjustment value designated by the take-in portion
14
.
In a prior art example of the ATM cell multiplexer as shown in
FIG. 12
, when there are two cards, each of which has an FIFO composed of two RAM's, and the cells are accumulated in both FIFO's, a “skip polling” operation by which the ATM cells are alternately read from the FIFO's has been performed.
Since the skip polling operation is performed to the FIFO's of both cards {circle around (1)} and {circle around (2)} when the ATM cells are read in such a conventional ATM cell multiplexer, the write/read processing of FIFO is performed preferentially to the cells arrived earlier in each of the cards. However, in both cards the cells are not always read in the order in which the cells have been written in the FIFO's due to the read timing of the ATM-PON layer and the like. Therefore, it has been disadvantageous that the oldest cell is not always read first.
Also when the ATM cells in the FIFO corresponding to a single card are almost fully occupied, it takes time to write the ATM cell, so that there has been a problem that the maximum waiting time is elongated when the mapping on the ATM-PON layer to the ATM cell is performed.
Furthermore, since no priority degree of the ATM cell from the card is identified, services of data system for data and the like and real time system for telephone and the like can not be separated when they exist together in a single card, so that there has been a problem that only the ATM cells of the real time system can not be preferentially transferred.
Moreover, the card may be pulled out during the operation. In this case, there has been a problem that an unnecessary ATM cell is to be read from the FIFO corresponding to the card pulled out with the inserted card being kept as it is.
SUMMARY OF THE INVENTION
It is accordingly an object of the present invention to provide an ATM cell multiplexer which multiplexes ATM cells outputted from a plurality of cards and which preferentially transfers the oldest ATM cell with a less waiting time.
In order to achieve the above-mentioned object, an ATM cell multiplexer including a plurality of memories connected to the cards, write processors which add sequential cell arrival numbers common to each of the cards to the ATM cells to be written in the memories, and a read processor which reads the cell arrival numbers from the memories to check a sequentiality thereof, thereby reading the ATM cells from the cards in an order of the cell arrival numbers, and which makes the cell arrival numbers at that time the cell arrival numbers to be checked at a next read time.
Namely when the ATM cells from the cards are written in the corresponding memories, the write processors sequentially add the cell arrival numbers to the ATM cells to be written in the memories with the added cell arrival numbers. The cell arrival numbers are sequential numbers common to each of the cards.
The read processor reads only each of the cell arrival numbers added to the ATM cells. By comparing this with the cell arrival number previously read, the read processor reads the ATM cell which has the cell arrival number sequential to that previously read since it is the next ATM cell to be read, so that the cell arrival number of the ATM cell is made the cell arrival number to be checked at the next read time.
Thus, even if there are a plurality of cards, it becomes possible to process a read order of the ATM cells in the order of arrival by using the sequentiality of the cell arrival numbers.
In the ATM cell multiplexer when detecting that the ATM cells from the cards have simultaneously arrived, the write processors may add identical cell arrival numbers to the ATM cells to be written in the memories, and the read processor may preferentially read the ATM cells of a predetermined card from a corresponding memory.
Namely when the ATM cells have simultaneously arrived from the cards, the write processors add common and identical cell arrival numbers to the ATM cells. When reading the cell arrival numbers added to the ATM cells, the read processor preferentially reads from a memory corresponding to a predetermined card. Thus, it becomes possible to realize a skip polling to every memory.
In the ATM cell multiplexer the memories may be divided into a number corresponding to a priority degree, the write processors may detect the priority degree preliminarily added to the ATM cells and add the cell arrival numbers to the ATM cells according to the priority degree to be written in the corresponding memories, and the read processor may read the ATM cells in the order of the cell arrival numbers from the ATM cells in the memory whose priority degree is high.
Namely when a priority identification bit or the like indicating the priority degree is added to the ATM cell, the priority degree of the ATM cell is identified by the identification bit, and is classified into e.g. a high priority for the real time system and a low priority for the data system. By writing the ATM cell in the memories corresponding to the cards according to the priority degree, the cell arrival numbers are independently set according to the priority degree.
The read processor confirms whether or not there are written cells in the memory whose priority degree is high. If so, then the ATM cells are read according to the above-mentioned cell arrival numbers. If not so, then the ATM cells are read from the memory whose priority degree is low. Also in this case, the ATM cells are read according to the cell arrival numbers.
Thus, while there are ATM cells with the high priority degree left in the memory, reading them from the memory is continued. When there is no ATM cell with the high priority degree left, the ATM cells with the low priority degree are read. Thus, it becomes possible to earlier read the ATM cells with the high priority degree without being influenced by the ATM cells with the low priority degree.
In the ATM cell multiplexer the write processors may have an address counter at a time of writing the ATM cells in the memories, and make the corresponding address counter count up and notify the count value to the read processor when the ATM cells are written in the memories, and the read processor may have an address counter at a time of reading corresponding to the former address counter, and make the corresponding address counter count up and determine whether or not the AT

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