ATM cell multiplexer

Details ATM cell multiplexer ATM cell multiplexer

1999-01-06

2003-08-26

Patel, Alm (Department: 2664)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S395600

Reexamination Certificate

active

06611523

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an ATM cell multiplexer, and in particular to an ATM cell multiplexer connected between terminal equipments and an ATM switchboard.
“ATM (Asynchronous Transfer Mode)” technology is expected as a communication technology for realizing a multi-media society, and has been developed for fast data used in an inter-computer communication etc.
However, as seen from recent ATM forums, a network is demanded in the market where the communication protocols of prior art such as for voices, HDLC (High level Data Link) and FR (frame relay) can also be interworked with the ATM technology.
When such a network is constructed, it is useful to set up an ATM cell multiplexer as an apparatus in branch circuit or line system in order to construct an ATM switchboard (ATM switch) as a key network and to increase the accommodation efficiency of circuits with terminal equipments.
2. Description of the Related Art
FIG. 52
shows a general arrangement of such an ATM cell multiplexer. An ATM cell multiplexer generally designated by reference numeral
2
is adapted to assemble data received from a terminal equipment generally designated by reference numeral
1
in the form of an ATM cell, to send the data to an ATM switchboard generally designated by reference numeral
3
through a trunk circuit, and to disassemble the ATM cell (hereinafter simply referred to as the cell) which is received through the trunk circuit from the ATM switchboard
3
and transmitted to the terminal equipment
1
.
In this ATM cell multiplexer, although strict traffic control (QOS control) proper to the ATM protocol is demanded, the prior art ATM switchboard and ATM cell multiplexer has installed an ATM switch (not shown) to perform the traffic control.
However, the ATM switch is disadvantageous in that the manufacturing cost is highly expensive and the control of the software/hardware is complicated, requiring a large-sized unit.
While an ATM cell multiplexer such as shown in the Japanese Patent Laid-open Publication No.5-91126 has been proposed, it requires the output capacity for the whole circuits because of adopting a method in which cells are simply multiplexed.
In addition, an ATM cell multiplexer such as shown in the Japanese Patent Laid-open Publication No.7-38569 uses a plurality of CLAD units which include both functions of cellulating data received from the terminal equipments and decellulating the cells received from the trunk circuits. However, when the cells through a plurality of connections mutually compete within the ATM cell multiplexer, some of the cells must be delayed or stood by to make the cells communicate without any collision in each of service categories such as CBR (Constant Bit Rate), VBR (Variable Bit Rate), or UBR (Unspecific Bit Rate).
This is not particularly allowed in a service category like CBR in which a time delay is strictly prohibited.
SUMMARY OF THE INVENTION
It is accordingly an object of the present invention to provide an ATM cell multiplexer which can simply and inexpensively assemble or disassemble cells without causing a time delay between terminal equipments and an ATM switchboard.
To achieve the above-mentioned object, an ATM cell multiplexer according to the present invention comprises a plurality of CLAD units, connected in parallel on an ATM bus so that ATM cells are assembled and disassembled between terminal equipments and the ATM switchboard, each including a cell holding portion, a communication controller, and a cell terminal portion which are all mutually connected with a Utopia Level 2 interface (hereinafter, occasionally referred to simply as “Utopia Level 2”), and an ATM bus scheduler for an ATM bus control connected to the CLAD units through the ATM bus; the cells from the cell terminal portion being held in the cell holding portion through the Utopia Level 2 under control of the communication controller for a cell transfer in the up direction from the terminal equipments to the ATM switchboard, and the ATM bus scheduler making the cell holding portion transmit the cells to the ATM bus by assigning a transmission right for every cell holding portion of the CLAD units in accordance with a preset schedule table based on at least one of predetermined service categories and a traffic control corresponding to a traffic quantity; and the cells being broadcast from the ATM bus to the cell holding portion of each CLAD unit for a cell transfer in the down direction from the ATM switchboard to the terminal equipments, and the communication controller making the cell holding portion transfer the cells to the cell terminal portion through the Utopia Level 2 to decide whether or not the cells are addressed to itself.
Namely, in order to efficiently and easily multiplex the ATM cell transmitted from a plurality of CLAD units, the ATM cell multiplexer according to the present invention, as schematically shown in
FIG. 1
, is provided therein with an ATM bus
12
, to which CLAD units
13
-
1
-
13
-
n
(hereinafter occasionally referred to as “13”) are connected in parallel to enable the cell to be transmitted to a trunk circuit or a backup circuit thereof from the CLAD units
13
through a trunk circuit controller
14
or a backup circuit controller
15
, respectively.
Also, in order to provide an opportunity of transmitting the cells out of the CLAD units
13
, an ATM bus scheduler
11
is connected to the ATM bus
12
. This ATM bus scheduler
11
performs cell multiplexing operations and traffic controls without installing any ATM switch by controlling the transmission/reception of the cells on the ATM bus
12
.
In this case, “schedule” means that the ATM bus scheduler
11
assigns a transmission right of cells to each of the CLAD units
13
so that the cells may be transmitted to the ATM switchboard (see
FIG. 1
) from the CLAD units
13
through the trunk circuit.
The CLAD units
13
accommodate terminal circuits connected to the terminal equipments (see FIG.
1
), and assemble data received from the terminal equipments in the form of cell which is to be transmitted to the ATM bus
12
. The cells received from the ATM switchboard through the trunk circuit are also transmitted to the ATM bus
12
and each of the CLAD units
13
.
The role of the ATM bus
12
is an interface between an ATM layer (a network layer) in the CLAD units
13
and a physical layer by a physical layer terminal portion (PHY)
10
in the circuit controllers
14
and
15
. For this function, the CLAD units
13
are provided with an ATM cell terminal portion
20
represented by an SAR (Segmentation And Reassembly) including a function of assembling and disassembling ATM cells.
Also, as the above-mentioned interface a Utopia Level 2 is adopted, which is a standard interface prescribed by the ATM forum and is known as what achieves data transfer with the physical layer terminal portion
10
individually connected to the ATM cell terminal portion
20
, as shown in FIG.
2
. Hereinafter, apart from the arrangement in
FIG. 1
, the Utopia Level 2 per se will be described referring to
FIGS. 2-4
.
Transmission of Cells from ATM Layer to Physical Layer Terminal Portion
10
: see
FIG. 3
A signal TxCav from the physical layer terminal portion
10
to the ATM cell terminal portion
20
of the CLAD units
13
is one for indicating that the physical layer terminal portion
10
can receive the cells.
When a transmitting cell exists inside the ATM cell terminal portion
20
and the signal TxCav indicates that the physical layer terminal portion
10
is in a reception enable state, based on a clock signal CLK, the ATM cell terminal portion
20
transmits cell data TxData composed of data Data01-Data53 with a signal TxEnb asserted or enabled (an inverted TxEnb deasserted or disabled).
A signal TxSoc is also asserted at the time of the head data01 in the cell data TxData. The cell data TxData is transmitted while the signal TxEnb is asserted.
Transmission of Cells from Physical Layer Terminal Portion
10
to ATM Layer: see
FIG. 4
A signal RxC

Affiliated with

Also associated with

Rating

ATM cell multiplexer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with ATM cell multiplexer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and ATM cell multiplexer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3089456