ATM cell delay circuit for ISDN system

Details ATM cell delay circuit for ISDN system ATM cell delay circuit for ISDN system

1993-07-30

1994-05-03

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370102, 370108, H04J 306, H04J 324

Patent

active

053094387

ABSTRACT:
A circuit for applying delays to ATM cells in an ISDN comprises a dummy cell generating circuit for generating dummy cells at a controllable time interval, a first cell filter for extracting from an input signal only those cells to which delays are to be applied, a cell multiplexing circuit for synthesizing an output of the dummy cell generating circuit and an output of the cell filter, a delay adding circuit for delaying an output of the cell multiplexing circuit, and a second cell filter for eliminating the dummy cells from the output of the delay adding circuit. In case the dummy cell generating circuit is arranged to generate idle cells, the second cell filter is omitted. By multiplexing the signal cells inputted to the delay adding circuit with the dummy cells, the time taken for the input cells to pass through a shift register constituting the delay adding circuit can be controlled.

REFERENCES:
patent: 4353129 (1982-10-01), Nishiwaki
patent: 4594706 (1986-06-01), Kobayashi
patent: 4970720 (1990-11-01), Esaki
patent: 5130978 (1992-07-01), Mobasser
Murakami, H.; Yokoi, T.; Taka, M.; "Considerations on ATM Networking Performance Planning", IEICE Trans. Commun.; vol. E75-B, No. 7; Jul. 1992; pp. 563-571.
Uematsu, H.; Ueda, H.; "STM Signal Transfer Techniques in ATM Networks", IEEE Communications Society Reprint; 1992; No. 311.6

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