ATM cell buffer circuit and priority order allocating method...

Details ATM cell buffer circuit and priority order allocating method... ATM cell buffer circuit and priority order allocating method...

1998-04-20

2001-10-09

Chin, Wellington (Department: 2664)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S416000, C370S230000

Reexamination Certificate

active

06301253

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an ATM cell switching device and, more particularly, to an ATM cell buffer circuit and a priority order allocating method at an ATM switching system which conduct priority control of the order of ATM cell transmission at the time of occurrence of ATM cell congestion.
2. Description of the Related Art
One of conventional ATM cell buffer circuits of this kind is, for example, the ATM cell buffer circuit disclosed in Japanese Patent Laying-Open (Kokai) No. Heisei 7-297840, entitled “Priority Controlling Method at Output Buffer Type ATM Switch”. The ATM cell buffer circuit recited in the literature, which is disposed at an input line unit located at the preceding stage of a switch unit in an ATM switching system, conducts reduction of a cell discard rate and control of a cell transmission delay in the ATM switching system according to a cell discard rate and a cell transmission delay time limit required for each connection.
FIG. 4
is a block diagram showing structure of a conventional ATM cell buffer circuit. As illustrated in
FIG. 4
, the ATM buffer circuit includes an input buffer unit
100
provided for each line and an output buffer type ATM switch
200
. The input buffer unit
100
conducts priority control based on a discard quality class and a delay quality class assigned to an input cell as a parameter. The output buffer type ATM switch
200
conducts switching based on routing information (output port number and other information) stored in an input cell. The switch also outputs a cell according to a transmission capacity of the output side.
The output buffer type ATM switch
200
includes a switch unit
210
, output buffer units
220
and congestion monitoring units
230
connected to the respective output buffer units. The switch unit
210
switches (self-switching) a cell received from each input buffer
100
through an input port to a predetermined output port based on routing information assigned to the cell. The output buffer unit
220
is provided for each output port of the switch unit
210
and has a plurality of buffer memories therein corresponding to the order of priority based on delay quality classes. The congestion monitoring unit
230
is provided for each output buffer
220
and outputs an output buffer threshold value exceeding signal S
0
when the amount of cells accumulated in the buffer memory in each output buffer unit
220
exceeds a predetermined threshold value. The output buffer threshold value exceeding signal S
0
output from the congestion monitoring unit
230
is fed back to the input buffer unit
100
.
The input buffer unit
100
includes a write control unit
120
, queues
110
and a read control unit
130
. The queue
110
is a logic queue virtually provided, in a buffer memory, corresponding to a delay quality class and each output port of the switch unit
210
for temporarily storing an input cell. The write control unit
120
writes an input cell to a queue
110
corresponding to a delay quality class and an output port number assigned to the input cell according to the amount of cells accumulated in each queue
110
. The read control unit
130
receives input of the amount of cells accumulated in each queue
110
and an output buffer threshold value exceeding signal S
0
output from the congestion monitoring unit
230
, and reads and transmits a cell from a predetermined queue
110
to the switch unit
210
in response to the output buffer threshold value exceeding signal S
0
.
FIG. 5
is a diagram for use in explaining reading priority order based on delay quality classes in the ATM cell buffer circuit of FIG.
4
. With reference to
FIG. 5
, a discard quality class and a delay quality class assigned to an input cell are represented by a matrix of priority class CL (x, y). The figure shows that the lower the discard quality class x assigned to an input cell is, the more liable the cell is to be discarded to have a higher discard rate and that to the contrary, the higher the discard quality class x is, the less liable the cell is to be discarded to have a lower discard rate. The figure also shows that the lower a delay quality class y is, the harder the cell is to be read to have a longer delay time and that to the contrary, the higher the delay quality class y is, the easier the cell is to be read to have a shorter delay time.
Description will be next made of operation of the read control unit
130
in the input buffer unit
100
with reference to FIG.
5
. At each input buffer unit
100
, the queues
110
are logically divided into (the number of output ports of the switch unit
210
: N)×(the number of initial delay quality classes: y−2). Assuming that delay quality classes in
FIG. 5
are ‘1’ to ‘4’, an initial delay quality class of each queue
110
is fixedly determined to be ‘2’ or ‘3’ at the initial setting of the ATM switch. This value can not be modified.
The read control unit
130
has a state control table to be referred to for the reading of cells from the queues
110
and controls such that when the number of cells accumulated in each queue
110
exceeds a threshold value, a delay quality class of the queue
110
is upgraded from ‘2’ to ‘3’ or from ‘3’ to ‘4’ and on the reception of an output buffer threshold value exceeding signal from the congestion monitoring unit
230
, the value of a delay quality class of a queue
110
corresponding to the output port in question is reduced to “1”. Cell reading is conducted by sequentially confirming whether cells are accumulated in the queues
110
in the descending order of the classes, starting with a queue
110
whose delay quality class is ‘4’, the highest, and reading cells of a queue
110
of a class in question when cells are accumulated. When there exist a plurality of queues
110
of the same delay quality class where cells are accumulated, one queue
110
is equally selected under round robin priority control, from which cells are read. When no cell is accumulated in queues
110
whose delay quality class values are ‘4’, ‘3’, and ‘2’ and cells are accumulated in a queue
110
whose delay quality class value is ‘1’, idle cells are transmitted to the switch unit
210
without execution of cell reading from the queue
110
.
The above-described conventional ATM cell buffer circuit, however, has a drawback that in a state where services are being provided without using all the delay quality classes which the ATM cell switching device has, when service of a new delay quality class is to be added, if the delay quality class to be assigned to the additional service fails to coincide with an unused delay quality class, such laborious work is necessary as suspension of the service of a delay quality class which is already being provided or re-routing of connections because relative positioning of the priority for reading cells from the respective queues
110
is fixed.
Further description will be made with respect to a concrete example. It is assumed that the respective queues
110
at the input buffer unit
100
have three delay quality classes which are referred to as Qos#1, Qos#2 and Qos#3, respectively. Assuming that the number of delay quality classes of the queues
110
is three, a value of the delay quality class y managed by the read control unit
130
ranges from ‘1’ to ‘5’ and a value of the initial delay quality class to be assigned to the three delay quality classes will accordingly range from ‘2’ to ‘4’. If at the start of the services, only two of the three delay quality classes need to be used and when at the time of addition of an unused delay quality class, its priority over the existing two delay quality classes is unknown, conditions of using two classes among the initial delay quality class values from ‘2’ to ‘4’ can not be determined. Therefore, it is assumed that a delay quality class with the value of ‘2’ whose reading priority is low is not to be used and delay quality classes with the values of ‘3’ and ‘4’ are to be used. As described above, it i

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