Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2000-02-08
2003-10-21
Olms, Douglas (Department: 2661)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S395600, C370S395620, C370S473000, C370S474000
Reexamination Certificate
active
06636517
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an ATM (asynchronous transfer mode) cell assembling/disassembling apparatus provided at an ATM terminal on an ATM network.
2. Description of the Related Art
In general, an ATM cell assembling/disassembling apparatus is provided on an ATM terminal connected to an ATM network. In this ATM cell assembling/disassembling apparatus, as a configuration for realizing a reception function, a 53-byte reception ATM cell sent from a physical layer device is disassembled into a 5-byte header data and 48-byte payload data. Furthermore, from a plurality of payloads, a reception packet is formed per virtual channel (hereinafter, referred to as VC) for use for passing to an upper layer application.
Moreover, for realizing a transmission function, a transmission packet formed by an upper layer application is divided into 48-byte payloads, and a 5-byte header is added to each of the payloads so as to be transmitted to a physical layer device.
FIG. 9
is a block diagram showing a conventional ATM cell assembling/disassembling apparatus. As shown in
FIG. 9
, an ATM cell assembling/disassembling apparatus
101
is connected to a physical layer device
5
that performs transmission and reception of a frame data to/from an ATM network.
On the other hand, the ATM cell assembling/disassembling apparatus
101
is connected via a host bus
4
to a host CPU
2
for operating an upper layer application and to a host memory
3
for storing a transmission and reception packet. The host CPU
2
also performs management of the host memory
3
and issues commands to the ATM cell assembling/disassembling apparatus
101
.
The ATM cell assembling/disassembling apparatus
101
includes: a cell reception/disassembling block
106
for performing cell reception and disassembling; a cell assembling/transmission block
107
for performing assembling of a transmission cell and transmission of the cell; and a reception VC address-transmission/reception parameter storage block
109
for storing information required for transmission and reception.
In general, a semiconductor memory is used for the reception VC address-transmission/reception parameter storage block
109
. Moreover, a memory interface block
108
performing memory access control is provided together with the VC address-transmission/reception parameter storage block
109
.
The cell reception/disassembly block
106
is constituted by: a reception controller
120
mainly performing a cell reception and cell disassembling; and a reception data buffer
121
for temporarily storing a 48-byte payload data extracted from a cell by the reception controller
120
.
The cell assembly/transmission block
107
performing cell assembling and transmission is constituted by transmission controller
125
mainly performing a cell assembling and transmission; and a transmission data buffer
126
for temporarily storing a 48-byte payload data which is used for the cell assembling performed by the transmission controller
125
.
Furthermore, the ATM cell assembling/disassembling apparatus
101
, for realizing an interface function with a physical layer device, includes: a cell reception interface
110
for receiving an ATM cell from a physical layer device
5
, and a cell transmission interface
111
for transmitting an ATM cell to the physical layer device
5
.
Moreover, the ATM cell assembling/disassembling apparatus
101
realizes an interface function for the host system by comprising: a host access block
114
for register access from the host CPU
2
and an command to the ATM cell assembling/disassembling apparatus
101
; and a DMA output block
112
and a DMA input block
113
for DMA (direct memory access) data transfer to the host memory
3
.
FIG. 10
is a flowchart explaining a reception operation by the ATM cell assembling/disassembling apparatus
101
. Hereinafter, explanation will be given on the reception operation of the ATM cell assembling/disassembling apparatus
101
shown in
FIG. 9
, referring to FIG.
10
.
When an ATM cell is received from the physical layer device
5
by the cell reception interface
110
, the reception controller
120
references a VC identification code VPI/VCI in the 5-byte cell header. According to this VPI/VCI, the reception controller
120
determines whether the received cell belongs to a VC which the upper layer application operating on the host CPU
2
wants to receive (hereinafter, this VC will be referred to as a valid reception VC and the cell will be referred to as a valid reception cell).
The valid reception VC has been stored in the reception VC address-transmission/reception parameter storage block
109
.
If the cell passed from the cell reception interface
110
is a valid reception cell, i.e., which VC is stored in the reception VC address-transmission/reception parameter storage block
109
, the reception controller
120
determines to perform reception. Moreover, if the cell passed from the cell reception interface
110
is a cell of a VC not stored in the reception VC address-transmission/reception parameter storage block
109
, or a cell in which VCI/VPI are all zeros (hereinafter, referred to as an invalid reception cell), the reception controller
120
determines not to perform reception (step S
51
).
When step S
51
has determined to perform reception, the reception controller
120
reads out a reception parameter related to this VC stored in the reception VC address-transmission/reception parameter storage block
109
(step S
52
), and performs cell disassembling and error detection according to the parameter (step S
53
). Subsequently, the reception controller
120
stores the 48-byte payload data extracted from the cell, in the reception data buffer
121
and requests the DMA output block
112
to perform DMA transmission of the reception payload data (step S
54
).
The reception payload data stored in the reception data buffer
121
is DMA-transferred to the host memory
3
by the DMA output block
112
(step S
55
). This completes one cell reception processing.
It should be noted that if the reception cell is determined to be an invalid reception cell in step S
51
, the reception controller
120
discards the cell without performing the processes of steps S
52
to S
55
, thus completing one cell reception processing (step S
56
).
The aforementioned processing is performed each time the cell reception interface
110
receives an ATM cell from the physical layer device
5
, and the reception payload data transferred to the host memory
3
is assembled into a packet.
FIG. 11
is a flowchart explaining a transmission operation of the ATM cell assembling/disassembling apparatus
101
of FIG.
9
. Hereinafter, explanation will be given on the transmission operation of the ATM cell assembling/disassembling apparatus
101
of
FIG. 9
, referring to FIG.
11
.
Firstly, the transmission controller
125
determines a VC of a cell to be transmitted next according to a transmission rate information of the respective VC, i.e., valid VC (hereinafter, this VC will be referred to as a valid transmission VC and the cell will be referred to as a valid transmission cell). This decision is made for each of the cells and sometimes, in order to adjust the transmission rate, a pseudo cell in which VPI/VCI are all zeroes may be decided to be transmitted (step S
61
).
Next, the transmission controller
125
branches the processing depending whether the VC determined in step S
61
is a valid transmission VC or pseudo cell transmission (step S
62
).
If the VC determined in step S
61
is a valid transmission VC, the transmission controller
125
reads out a transmission parameter of the VC to be transmitted and according to the transmission parameter, determines a storage address of the transmission payload data in the host memory
3
. According to this address, the transmission controller
125
requests the DMA input block
113
to DMA-transfer the payload data of one cell from the host memory
3
(step S
63
).
The DMA input block
113
, by the DMA transf
NEC Electronics Corporation
Olms Douglas
Wilson Robert W.
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