ATM apparatus, IP apparatus and bus system

Details ATM apparatus, IP apparatus and bus system ATM apparatus, IP apparatus and bus system

2006-06-06

2006-06-06

Qureshi, Afsar (Department: 2667)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S362000, C370S395520, C370S455000

Reexamination Certificate

active

07058060

ABSTRACT:
Arbitration for a bus mastership is performed in accordance with the priority degrees of data which are to be transferred on a bus, by a comparatively simple construction. In a case where interfaces2, 3simultaneously output to the bus1the priority degrees which correspond to non-ATM lines6, 7being the reception sources or transmission destinations of the data stored in ATM cells, and where the priority degrees outputted by the interface themselves are the highest, the interfaces transmit to the bus1, bus mastership request signals which contain the addresses of the interfaces themselves. A bus control module4receives the bus mastership request signals on the bus1, it determines that one of the interfaces to which the bus mastership is granted, and it outputs to the bus1a bus mastership grant signal which contains the address of the determined interface.

REFERENCES:
patent: 5619500 (1997-04-01), Hiekali
patent: 6667977 (2003-12-01), Ono
patent: 2001/0036202 (2001-11-01), Watanabe et al.

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