ATD pulse generator circuit with ECL to CMOS level conversion

Details ATD pulse generator circuit with ECL to CMOS level conversion ATD pulse generator circuit with ECL to CMOS level conversion

1992-08-12

1994-07-12

LaRoche, Eugene R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307455, 3652335, H03K 190175, G11C 800

Patent

active

053291824

ABSTRACT:
An ATD pulse generator circuit (20) provides an ATD pulse at CMOS logic levels in response to a single-ended ECL level input signal transition. An emitter-follower input portion (21), a differential amplifier (23), and emitter-follower portion (25) converts the single-ended input signal to intermediate level differential signals. P-channel transistors (51 and 52) receive the intermediate level differential signals and provide complementary CMOS level outputs signals. Cross-coupled delay portion (29) prevents the N-channel transistors (55 and 56) from switching on until after a delay, causing both of the CMOS level output signals to remain at logic high levels for a predetermined time. Cross-coupling the N-channel transistors (55 and 56) also results in reduced power consumption. A NAND gate (31) receives the logic high levels and provides a CMOS level ATD pulse, the duration of which is adjustable.

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patent: 5059829 (1991-10-01), Flannagan et al.
patent: 5075581 (1991-12-01), Kamata
patent: 5124584 (1992-06-01), McClure
patent: 5140191 (1992-08-01), Nogle et al.
patent: 5233565 (1993-08-01), Wang

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