At-speed on-chip short clock cycle monitoring system and method

Details At-speed on-chip short clock cycle monitoring system and method At-speed on-chip short clock cycle monitoring system and method

2006-10-31

2006-10-31

Nguyen, Vincent Q. (Department: 2858)

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

Frequency of cyclic current or voltage

C324S076540, C327S292000

Reexamination Certificate

active

07129690

ABSTRACT:
The present invention provides a system and method for monitoring a short clock cycle on a semiconductor chip. The system includes a phase-locked loop (PLL) for receiving a reference clock as input and for outputting a PLL clock out. The system includes a delay-locked loop (DLL) for receiving the PLL clock out as input and for outputting a DLL phase offset clock. The DLL is locked to a frequency of the PLL clock out. The system may include an edge comparator for receiving the PLL clock out and the DLL phase offset clock as input. The edge comparator is suitable for monitoring each edge of the PLL clock out and each edge of the DLL phase offset clock, and for reporting a short clock cycle when an edge of the PLL clock out comes before an edge of the DLL phase offset clock.

REFERENCES:
patent: 2005/0012524 (2005-01-01), Green et al.
patent: 2005/0063502 (2005-03-01), Ware et al.

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